Code cleanup ad improvement.

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_bus.h

@@ -1,1313 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_bus.h
-  * @author  MCD Application Team
-  * @brief   Header file of BUS LL module.
-
-  @verbatim
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]
-      A delay between an RCC peripheral clock enable and the effective peripheral
-      enabling should be taken into account in order to manage the peripheral read/write
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-        (++) AHB & APB peripherals, 1 dummy read is necessary
-
-    [..]
-      Workarounds:
-      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_BUS_H
-#define STM32G0xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
-  * @{
-  */
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHBENR_DMA1EN
-#if defined(DMA2)
-#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHBENR_DMA2EN
-#endif /* DMA2 */
-#define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHBENR_FLASHEN
-#define LL_AHB1_GRP1_PERIPH_SRAM           RCC_AHBSMENR_SRAMSMEN
-#if defined(CRC)
-#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHBENR_CRCEN
-#endif /* CRC */
-#if defined(AES)
-#define LL_AHB1_GRP1_PERIPH_CRYP           RCC_AHBENR_AESEN
-#endif /* AES */
-#if defined(RNG)
-#define LL_AHB1_GRP1_PERIPH_RNG            RCC_AHBENR_RNGEN
-#endif /* RNG */
-/**
-  * @}
-  */
-
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#if defined(TIM2)
-#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APBENR1_TIM2EN
-#endif /* TIM2 */
-#if defined(TIM3)
-#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APBENR1_TIM3EN
-#endif /* TIM3 */
-#if defined(TIM4)
-#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APBENR1_TIM4EN
-#endif /* TIM4 */
-#if defined(TIM6)
-#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APBENR1_TIM6EN
-#endif /* TIM6 */
-#if defined(TIM7)
-#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APBENR1_TIM7EN
-#endif /* TIM7 */
-#if defined(LPUART2)
-#define LL_APB1_GRP1_PERIPH_LPUART2        RCC_APBENR1_LPUART2EN
-#endif /* LPUART2 */
-#if defined(USART5)
-#define LL_APB1_GRP1_PERIPH_USART5         RCC_APBENR1_USART5EN
-#endif /* USART5 */
-#if defined(USART6)
-#define LL_APB1_GRP1_PERIPH_USART6         RCC_APBENR1_USART6EN
-#endif /* USART6 */
-#define LL_APB1_GRP1_PERIPH_RTC            RCC_APBENR1_RTCAPBEN
-#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APBENR1_WWDGEN
-#if defined(FDCAN1) || defined(FDCAN2)
-#define LL_APB1_GRP1_PERIPH_FDCAN          RCC_APBENR1_FDCANEN
-#endif /* FDCAN1 */
-#if defined(USB_DRD_FS)
-#define LL_APB1_GRP1_PERIPH_USB            RCC_APBENR1_USBEN
-#endif /* USB_DRD_FS */
-#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APBENR1_SPI2EN
-#if defined(SPI3)
-#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APBENR1_SPI3EN
-#endif /* SPI3 */
-#if defined(CRS)
-#define LL_APB1_GRP1_PERIPH_CRS            RCC_APBENR1_CRSEN
-#endif /* CRS */
-#define LL_APB1_GRP1_PERIPH_USART2         RCC_APBENR1_USART2EN
-#if defined(USART3)
-#define LL_APB1_GRP1_PERIPH_USART3         RCC_APBENR1_USART3EN
-#endif /* USART3 */
-#if defined(USART4)
-#define LL_APB1_GRP1_PERIPH_USART4         RCC_APBENR1_USART4EN
-#endif /* USART4 */
-#if defined(LPUART1)
-#define LL_APB1_GRP1_PERIPH_LPUART1        RCC_APBENR1_LPUART1EN
-#endif /* LPUART1 */
-#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APBENR1_I2C1EN
-#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APBENR1_I2C2EN
-#if defined(I2C3)
-#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APBENR1_I2C3EN
-#endif /* I2C3 */
-#if defined(CEC)
-#define LL_APB1_GRP1_PERIPH_CEC            RCC_APBENR1_CECEN
-#endif /* CEC */
-#if defined(UCPD1)
-#define LL_APB1_GRP1_PERIPH_UCPD1          RCC_APBENR1_UCPD1EN
-#endif /* UCPD1 */
-#if defined(UCPD2)
-#define LL_APB1_GRP1_PERIPH_UCPD2          RCC_APBENR1_UCPD2EN
-#endif /* UCPD2 */
-#define LL_APB1_GRP1_PERIPH_DBGMCU         RCC_APBENR1_DBGEN
-#define LL_APB1_GRP1_PERIPH_PWR            RCC_APBENR1_PWREN
-#if defined(DAC1)
-#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APBENR1_DAC1EN
-#endif /* DAC1 */
-#if defined(LPTIM2)
-#define LL_APB1_GRP1_PERIPH_LPTIM2         RCC_APBENR1_LPTIM2EN
-#endif /* LPTIM2 */
-#if defined(LPTIM1)
-#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APBENR1_LPTIM1EN
-#endif /* LPTIM1 */
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APBENR2_SYSCFGEN
-#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APBENR2_TIM1EN
-#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APBENR2_SPI1EN
-#define LL_APB2_GRP1_PERIPH_USART1         RCC_APBENR2_USART1EN
-#if defined(TIM14)
-#define LL_APB2_GRP1_PERIPH_TIM14          RCC_APBENR2_TIM14EN
-#endif /* TIM14 */
-#if defined(TIM15)
-#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APBENR2_TIM15EN
-#endif /* TIM15 */
-#if defined(TIM16)
-#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APBENR2_TIM16EN
-#endif /* TIM16 */
-#if defined(TIM17)
-#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APBENR2_TIM17EN
-#endif /* TIM17 */
-#if defined(ADC)
-#define LL_APB2_GRP1_PERIPH_ADC            RCC_APBENR2_ADCEN
-#endif /* ADC */
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH  IOP GRP1 PERIPH
-  * @{
-  */
-#define LL_IOP_GRP1_PERIPH_ALL             0xFFFFFFFFU
-#define LL_IOP_GRP1_PERIPH_GPIOA           RCC_IOPENR_GPIOAEN
-#define LL_IOP_GRP1_PERIPH_GPIOB           RCC_IOPENR_GPIOBEN
-#define LL_IOP_GRP1_PERIPH_GPIOC           RCC_IOPENR_GPIOCEN
-#define LL_IOP_GRP1_PERIPH_GPIOD           RCC_IOPENR_GPIODEN
-#if defined(GPIOE)
-#define LL_IOP_GRP1_PERIPH_GPIOE           RCC_IOPENR_GPIOEEN
-#endif /* GPIOE */
-#if defined(GPIOF)
-#define LL_IOP_GRP1_PERIPH_GPIOF           RCC_IOPENR_GPIOFEN
-#endif /* GPIOF */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
-  * @{
-  */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB1 peripherals clock.
-  * @rmtoll AHBENR       DMA1EN        LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       FLASHEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       CRCEN         LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       AESEN         LL_AHB1_GRP1_EnableClock\n
-  *         AHBENR       RNGEN         LL_AHB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
-  * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
-  * @retval None
-  */
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHBENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB1 peripheral clock is enabled or not
-  * @rmtoll AHBENR       DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       FLASHEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       CRCEN         LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       AESEN         LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHBENR       RNGEN         LL_AHB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
-  * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
-  * @retval State of Periphs (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable AHB1 peripherals clock.
-  * @rmtoll AHBENR       DMA1EN        LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       FLASHEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       CRCEN         LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       AESEN         LL_AHB1_GRP1_DisableClock\n
-  *         AHBENR       RNGEN         LL_AHB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
-  * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
-  * @retval None
-  */
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHBENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB1 peripherals reset.
-  * @rmtoll AHBRSTR      DMA1RST       LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      FLASHRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      AESRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
-  * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
-  * @retval None
-  */
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB1 peripherals reset.
-  * @rmtoll AHBRSTR      DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      FLASHRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      AESRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
-  * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
-  * @retval None
-  */
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB1 peripheral clocks in Sleep and Stop modes
-  * @rmtoll AHBSMENR     DMA1SMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
-  *         AHBSMENR     FLASHSMEN     LL_AHB1_GRP1_EnableClockStopSleep\n
-  *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_EnableClockStopSleep\n
-  *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_EnableClockStopSleep\n
-  *         AHBSMENR     AESSMEN       LL_AHB1_GRP1_EnableClockStopSleep\n
-  *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_EnableClockStopSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
-  * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
-  * @retval None
-  */
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHBSMENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB1 peripheral clocks in Sleep and Stop modes
-  * @rmtoll AHBSMENR     DMA1SMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
-  *         AHBSMENR     FLASHSMEN     LL_AHB1_GRP1_DisableClockStopSleep\n
-  *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_DisableClockStopSleep\n
-  *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_DisableClockStopSleep\n
-  *         AHBSMENR     AESSMEN       LL_AHB1_GRP1_DisableClockStopSleep\n
-  *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_DisableClockStopSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG  (*)
-  * @note   (*) RNG & CRYP Peripherals available only on STM32G081xx
-  * @retval None
-  */
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHBSMENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
-  * @{
-  */
-
-/**
-  * @brief  Enable APB1 peripherals clock.
-  * @rmtoll APBENR1      TIM2EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      TIM3EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      TIM4EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      TIM6EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      TIM7EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      RTCAPBEN      LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      WWDGEN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      SPI2EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      SPI3EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      USART2EN      LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      USART3EN      LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      USART4EN      LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      USART5EN      LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      USART6EN      LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      LPUART1EN     LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      LPUART2EN     LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      I2C1EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      I2C2EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      I2C3EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      CECEN         LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      UCPD1EN       LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      UCPD2EN       LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      USBEN         LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      FDCANEN       LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      DBGEN         LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      PWREN         LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      DAC1EN        LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      LPTIM2EN      LL_APB1_GRP1_EnableClock\n
-  *         APBENR1      LPTIM1EN      LL_APB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
-  * @note Peripheral marked with (1) are not available all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APBENR1, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APBENR1, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB1 peripheral clock is enabled or not
-  * @rmtoll APBENR1      TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      USART2EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      USART3EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      USART4EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      USART5EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      USART6EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      LPUART1EN     LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      LPUART2EN     LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      CECEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      UCPD1EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      UCPD2EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      USBEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      FDCANEN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      DBGEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      PWREN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      DAC1EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      LPTIM2EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APBENR1      LPTIM1EN      LL_APB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
-  * @note Peripheral marked with (1) are not available all devices
-  * @retval State of Periphs (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock.
-  * @rmtoll APBENR1      TIM2EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      TIM3EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      TIM4EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      TIM6EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      TIM7EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      RTCAPBEN      LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      WWDGEN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      SPI2EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      SPI3EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      USART2EN      LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      USART3EN      LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      USART4EN      LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      USART5EN      LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      USART6EN      LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      LPUART1EN     LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      LPUART2EN     LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      I2C1EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      I2C2EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      I2C3EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      CECEN         LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      UCPD1EN       LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      UCPD2EN       LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      USBEN         LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      FDCANEN       LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      DBGEN         LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      PWREN         LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      DAC1EN        LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      LPTIM2EN      LL_APB1_GRP1_DisableClock\n
-  *         APBENR1      LPTIM1EN      LL_APB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
-  * @note Peripheral marked with (1) are not available all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APBENR1, Periphs);
-}
-
-/**
-  * @brief  Force APB1 peripherals reset.
-  * @rmtoll APBRSTR1     TIM2RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     TIM3RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     TIM4RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     TIM6RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     TIM7RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     RTCRST        LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     WWDGRST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     SPI2RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     SPI3RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     USART2RST     LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     USART3RST     LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     USART4RST     LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     USART5RST     LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     USART6RST     LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     LPUART1RST    LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     LPUART2RST    LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     I2C1RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     I2C2RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     I2C3RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     CECRST        LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     UCPD1RST      LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     UCPD2RST      LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     USBRST        LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     FDCANRST      LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     DBGRST        LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     PWRRST        LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     DAC1RST       LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     LPTIM2RST     LL_APB1_GRP1_ForceReset\n
-  *         APBRSTR1     LPTIM1RST     LL_APB1_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
-  * @note Peripheral marked with (1) are not available all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APBRSTR1, Periphs);
-}
-
-/**
-  * @brief  Release APB1 peripherals reset.
-  * @rmtoll APBRSTR1     TIM2RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     TIM4RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     TIM6RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     TIM7RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     RTCRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     WWDGRST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     SPI2RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     SPI3RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     USART2RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     USART3RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     USART4RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     USART5RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     USART6RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     LPUART1RST    LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     LPUART2RST    LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     I2C1RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     I2C2RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     I2C3RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     CECRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     UCPD1RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     UCPD2RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     USBRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     FDCANRST      LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     DBGRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     PWRRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     DAC1RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     LPTIM2RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APBRSTR1     LPTIM1RST     LL_APB1_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
-  * @note Peripheral marked with (1) are not available all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APBRSTR1, Periphs);
-}
-
-/**
-  * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes
-  * @rmtoll APBSMENR1    TIM2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    TIM3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    TIM4SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    TIM6SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    TIM7SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    RTCAPBSMEN    LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    WWDGSMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    SPI2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    SPI3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    USART2SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    USART3SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    USART4SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    USART5SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    USART6SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    LPUART1SMEN   LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    LPUART2SMEN   LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    I2C1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    I2C2SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    I2C3SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    CECSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    UCPD1SMEN     LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    UCPD2SMEN     LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    USBSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    FDCANSMEN     LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    DBGSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    PWRSMEN       LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    DAC1SMEN      LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    LPTIM2SMEN    LL_APB1_GRP1_EnableClockStopSleep\n
-  *         APBSMENR1    LPTIM1SMEN    LL_APB1_GRP1_EnableClockStopSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
-  * @note Peripheral marked with (1) are not available all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APBSMENR1, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APBSMENR1, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes
-  * @rmtoll APBSMENR1    TIM2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    TIM3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    TIM'SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    TIM6SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    TIM7SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    RTCAPBSMEN    LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    WWDGSMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    SPI2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    SPI3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    USART2SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    USART3SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    USART4SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    USART5SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    USART6SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    LPUART1SMEN   LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    LPUART2SMEN   LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    I2C1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    I2C2SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    I2C3SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    CECSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    UCPD1SMEN     LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    UCPD2SMEN     LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    USBSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    FSCANSMEN     LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    DBGSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    PWRSMEN       LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    DAC1SMEN      LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    LPTIM2SMEN    LL_APB1_GRP1_DisableClockStopSleep\n
-  *         APBSMENR1    LPTIM1SMEN    LL_APB1_GRP1_DisableClockStopSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTC
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART4  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART5  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART6  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD1   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UCPD2   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USB     (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FDCAN   (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1    (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2  (1)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1  (1)
-  * @note Peripheral marked with (1) are not available all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APBSMENR1, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
-  * @{
-  */
-
-/**
-  * @brief  Enable APB2 peripherals clock.
-  * @rmtoll APBENR2      SYSCFGEN      LL_APB2_GRP1_EnableClock\n
-  *         APBENR2      TIM1EN        LL_APB2_GRP1_EnableClock\n
-  *         APBENR2      SPI1EN        LL_APB2_GRP1_EnableClock\n
-  *         APBENR2      USART1EN      LL_APB2_GRP1_EnableClock\n
-  *         APBENR2      TIM14EN       LL_APB2_GRP1_EnableClock\n
-  *         APBENR2      TIM15EN       LL_APB2_GRP1_EnableClock\n
-  *         APBENR2      TIM16EN       LL_APB2_GRP1_EnableClock\n
-  *         APBENR2      TIM17EN       LL_APB2_GRP1_EnableClock\n
-  *         APBENR2      ADCEN         LL_APB2_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
-  * @note (*) peripheral not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APBENR2, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APBENR2, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB2 peripheral clock is enabled or not
-  * @rmtoll APBENR2      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APBENR2      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APBENR2      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APBENR2      USART1EN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APBENR2      TIM14EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APBENR2      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APBENR2      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APBENR2      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APBENR2      ADCEN         LL_APB2_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
-  * @note (*) peripheral not available on all devices
-  * @retval State of Periphs (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable APB2 peripherals clock.
-  * @rmtoll APBENR2      SYSCFGEN      LL_APB2_GRP1_DisableClock\n
-  *         APBENR2      TIM1EN        LL_APB2_GRP1_DisableClock\n
-  *         APBENR2      SPI1EN        LL_APB2_GRP1_DisableClock\n
-  *         APBENR2      USART1EN      LL_APB2_GRP1_DisableClock\n
-  *         APBENR2      TIM14EN       LL_APB2_GRP1_DisableClock\n
-  *         APBENR2      TIM15EN       LL_APB2_GRP1_DisableClock\n
-  *         APBENR2      TIM16EN       LL_APB2_GRP1_DisableClock\n
-  *         APBENR2      TIM17EN       LL_APB2_GRP1_DisableClock\n
-  *         APBENR2      ADCEN         LL_APB2_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
-  * @note (*) peripheral not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APBENR2, Periphs);
-}
-
-/**
-  * @brief  Force APB2 peripherals reset.
-  * @rmtoll APBRSTR2     SYSCFGRST     LL_APB2_GRP1_ForceReset\n
-  *         APBRSTR2     TIM1RST       LL_APB2_GRP1_ForceReset\n
-  *         APBRSTR2     SPI1RST       LL_APB2_GRP1_ForceReset\n
-  *         APBRSTR2     USART1RST     LL_APB2_GRP1_ForceReset\n
-  *         APBRSTR2     TIM14RST      LL_APB2_GRP1_ForceReset\n
-  *         APBRSTR2     TIM15RST      LL_APB2_GRP1_ForceReset\n
-  *         APBRSTR2     TIM16RST      LL_APB2_GRP1_ForceReset\n
-  *         APBRSTR2     TIM17RST      LL_APB2_GRP1_ForceReset\n
-  *         APBRSTR2     ADCRST        LL_APB2_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
-  * @note (*) peripheral not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APBRSTR2, Periphs);
-}
-
-/**
-  * @brief  Release APB2 peripherals reset.
-  * @rmtoll APBRSTR2     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\n
-  *         APBRSTR2     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APBRSTR2     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APBRSTR2     USART1RST     LL_APB2_GRP1_ReleaseReset\n
-  *         APBRSTR2     TIM14RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APBRSTR2     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APBRSTR2     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APBRSTR2     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APBRSTR2     ADCRST        LL_APB2_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
-  * @note (*) peripheral not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APBRSTR2, Periphs);
-}
-
-/**
-  * @brief  Enable APB2 peripheral clocks in Sleep and Stop modes
-  * @rmtoll APBSMENR2    SYSCFGSMEN    LL_APB2_GRP1_EnableClockStopSleep\n
-  *         APBSMENR2    TIM1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
-  *         APBSMENR2    SPI1SMEN      LL_APB2_GRP1_EnableClockStopSleep\n
-  *         APBSMENR2    USART1SMEN    LL_APB2_GRP1_EnableClockStopSleep\n
-  *         APBSMENR2    TIM14SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
-  *         APBSMENR2    TIM15SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
-  *         APBSMENR2    TIM16SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
-  *         APBSMENR2    TIM17SMEN     LL_APB2_GRP1_EnableClockStopSleep\n
-  *         APBSMENR2    ADCSMEN       LL_APB2_GRP1_EnableClockStopSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
-  * @note (*) peripheral not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APBSMENR2, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APBSMENR2, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB2 peripheral clocks in Sleep and Stop modes
-  * @rmtoll APBSMENR2    SYSCFGSMEN    LL_APB2_GRP1_DisableClockStopSleep\n
-  *         APBSMENR2    TIM1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
-  *         APBSMENR2    SPI1SMEN      LL_APB2_GRP1_DisableClockStopSleep\n
-  *         APBSMENR2    USART1SMEN    LL_APB2_GRP1_DisableClockStopSleep\n
-  *         APBSMENR2    TIM14SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
-  *         APBSMENR2    TIM15SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
-  *         APBSMENR2    TIM16SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
-  *         APBSMENR2    TIM17SMEN     LL_APB2_GRP1_DisableClockStopSleep\n
-  *         APBSMENR2    ADCSMEN       LL_APB2_GRP1_DisableClockStopSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM14
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
-  * @note (*) peripheral not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APBSMENR2, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_IOP IOP
-  * @{
-  */
-
-/**
-  * @brief  Enable IOP peripherals clock.
-  * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIOBEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIOCEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIODEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIOEEN       LL_IOP_GRP1_EnableClock\n
-  *         IOPENR       GPIOFEN       LL_IOP_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
-  * @retval None
-  */
-__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->IOPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->IOPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if IOP peripheral clock is enabled or not
-  * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIOBEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIOCEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIODEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIOEEN       LL_IOP_GRP1_IsEnabledClock\n
-  *         IOPENR       GPIOFEN       LL_IOP_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
-  * @retval State of Periphs (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Disable IOP peripherals clock.
-  * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIOBEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIOCEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIODEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIOEEN       LL_IOP_GRP1_DisableClock\n
-  *         IOPENR       GPIOFEN       LL_IOP_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
-  * @retval None
-  */
-__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->IOPENR, Periphs);
-}
-
-/**
-  * @brief  Disable IOP peripherals clock.
-  * @rmtoll IOPRSTR      GPIOARST      LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIOBRST      LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIOCRST      LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIODRST      LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIOERST      LL_IOP_GRP1_ForceReset\n
-  *         IOPRSTR      GPIOFRST      LL_IOP_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_ALL
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
-  * @retval None
-  */
-__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->IOPRSTR, Periphs);
-}
-
-/**
-  * @brief  Release IOP peripherals reset.
-  * @rmtoll IOPRSTR      GPIOARST      LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIOBRST      LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIOCRST      LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIODRST      LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIOERST      LL_IOP_GRP1_ReleaseReset\n
-  *         IOPRSTR      GPIOFRST      LL_IOP_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_ALL
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
-  * @retval None
-  */
-__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->IOPRSTR, Periphs);
-}
-
-/**
-  * @brief  Enable IOP peripheral clocks in Sleep and Stop modes
-  * @rmtoll IOPSMENR     GPIOASMEN     LL_IOP_GRP1_EnableClockStopSleep\n
-  *         IOPSMENR     GPIOBSMEN     LL_IOP_GRP1_EnableClockStopSleep\n
-  *         IOPSMENR     GPIOCSMEN     LL_IOP_GRP1_EnableClockStopSleep\n
-  *         IOPSMENR     GPIODSMEN     LL_IOP_GRP1_EnableClockStopSleep\n
-  *         IOPSMENR     GPIOESMEN     LL_IOP_GRP1_EnableClockStopSleep\n
-  *         IOPSMENR     GPIOFSMEN     LL_IOP_GRP1_EnableClockStopSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
-  * @retval None
-  */
-__STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->IOPSMENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable IOP peripheral clocks in Sleep and Stop modes
-  * @rmtoll IOPSMENR     GPIOASMEN     LL_IOP_GRP1_DisableClockStopSleep\n
-  *         IOPSMENR     GPIOBSMEN     LL_IOP_GRP1_DisableClockStopSleep\n
-  *         IOPSMENR     GPIOCSMEN     LL_IOP_GRP1_DisableClockStopSleep\n
-  *         IOPSMENR     GPIODSMEN     LL_IOP_GRP1_DisableClockStopSleep\n
-  *         IOPSMENR     GPIOESMEN     LL_IOP_GRP1_DisableClockStopSleep\n
-  *         IOPSMENR     GPIOFSMEN     LL_IOP_GRP1_DisableClockStopSleep
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
-  *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
-  * @retval None
-  */
-__STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->IOPSMENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* RCC */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_BUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_cortex.h

@@ -1,587 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_cortex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CORTEX LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL CORTEX driver contains a set of generic APIs that can be
-    used by user:
-      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
-          functions
-      (+) Low power mode configuration (SCB register of Cortex-MCU)
-      (+) MPU API to configure and enable regions
-      (+) API to access to MCU info (CPUID register)
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_CORTEX_H
-#define STM32G0xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX_LL CORTEX
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
-  * @{
-  */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
-  * @{
-  */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
-  * @{
-  */
-#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
-  * @{
-  */
-#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
-  * @{
-  */
-#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
-  * @{
-  */
-#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
-  * @{
-  */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
-  * @{
-  */
-
-/**
-  * @brief  This function checks if the Systick counter flag is active or not.
-  * @note   It can be used in timeout function on application side.
-  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
-{
-  return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configures the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
-{
-  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
-  {
-    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-  }
-  else
-  {
-    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-  }
-}
-
-/**
-  * @brief  Get the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
-{
-  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-}
-
-/**
-  * @brief  Enable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
-  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Disable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
-{
-  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
-{
-  return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
-  * @{
-  */
-
-/**
-  * @brief  Processor uses sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief  Processor uses deep sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
-{
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
-  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
-  *         empty main application.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief  Do not sleep when returning to Thread mode.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
-  *         processor.
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
-{
-  /* Set SEVEONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
-  *         excluded
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
-{
-  /* Clear SEVEONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
-  * @{
-  */
-
-/**
-  * @brief  Get Implementer code
-  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
-  * @retval Value should be equal to 0x41 for ARM
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
-  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
-  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
-  * @retval Value between 0 and 255 (0x0: revision 0)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
-}
-
-/**
-  * @brief  Get Architecture number
-  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetArchitecture
-  * @retval Value should be equal to 0xC for Cortex-M0+ devices
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
-  * @brief  Get Part number
-  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
-  * @retval Value should be equal to 0xC60 for Cortex-M0+
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
-}
-
-/**
-  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
-  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
-  * @retval Value between 0 and 255 (0x1: patch 1)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
-}
-
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
-  * @{
-  */
-
-/**
-  * @brief  Enable MPU with input options
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
-  * @param  Options This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
-  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
-  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
-{
-  /* Enable the MPU*/
-  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
-  /* Ensure MPU settings take effects */
-  __DSB();
-  /* Sequence instruction fetches using update settings */
-  __ISB();
-}
-
-/**
-  * @brief  Disable MPU
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Disable(void)
-{
-  /* Make sure outstanding transfers are done */
-  __DMB();
-  /* Disable MPU*/
-  WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
-  * @brief  Check if MPU is enabled or not
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
-{
-  return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable a MPU region
-  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Enable the MPU region */
-  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @brief  Configure and enable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
-  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @param  Address Value of region base address
-  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
-  * @param  Attributes This parameter can be a combination of the following values:
-  *         @arg @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
-  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
-  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
-  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
-  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
-  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
-  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
-  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
-  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
-  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
-  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
-  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
-  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Set base address */
-  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
-  /* Configure MPU */
-  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
-}
-
-/**
-  * @brief  Disable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
-  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Disable the MPU region */
-  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @}
-  */
-
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_CORTEX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h

@@ -1,2272 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_dma.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_DMA_H
-#define STM32G0xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-#include "stm32g0xx_ll_dmamux.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
-  * @{
-  */
-/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
-static const uint8_t CHANNEL_OFFSET_TAB[] =
-{
-  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
-#if defined(DMA1_Channel6_BASE)
-  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
-#endif /* DMA1_Channel6_BASE */
-#if defined(DMA1_Channel7_BASE)
-  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
-#endif /* DMA1_Channel7_BASE */
-};
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup DMA_LL_Private_Macros DMA Private Macros
-  * @{
-  */
-/**
-  * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @param  __DMA_INSTANCE__ DMAx
-  * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
-  */
-#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \
-(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
-/**
-  * @}
-  */
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
-  * @{
-  */
-typedef struct
-{
-  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
-                                        or as Source base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
-                                        or as Destination base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
-                                        from memory to memory or from peripheral to memory.
-                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
-
-  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
-                                        This parameter can be a value of @ref DMA_LL_EC_MODE
-                                        @note: The circular buffer mode cannot be used if the memory to memory
-                                               data transfer direction is configured on the selected Channel
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
-
-  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
-
-  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
-
-  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
-
-  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
-
-  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
-                                        The data unit is equal to the source buffer configuration set in PeripheralSize
-                                        or MemorySize parameters depending in the transfer direction.
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
-
-  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
-                                        This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
-
-  uint32_t Priority;               /*!< Specifies the channel priority level.
-                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
-
-} LL_DMA_InitTypeDef;
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
-  * @{
-  */
-/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_DMA_WriteReg function
-  * @{
-  */
-#define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
-#define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
-#define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
-#define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
-#define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
-#define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
-#define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
-#define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
-#define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
-#define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
-#if defined(DMA1_Channel6)
-#define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
-#define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-#define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
-#define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
-#define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
-#endif /* DMA1_Channel7 */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_DMA_ReadReg function
-  * @{
-  */
-#define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
-#define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
-#define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
-#define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
-#define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
-#define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
-#define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
-#define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
-#define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
-#define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
-#define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
-#define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
-#define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
-#define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
-#define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
-#define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
-#define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
-#define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
-#define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
-#define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
-#if defined(DMA1_Channel6)
-#define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
-#define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
-#define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
-#define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-#define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
-#define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
-#define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
-#define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
-#endif /* DMA1_Channel7 */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
-  * @{
-  */
-#define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
-#define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
-#define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
-  * @{
-  */
-#define LL_DMA_CHANNEL_1                  0x00000000U /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2                  0x00000001U /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3                  0x00000002U /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4                  0x00000003U /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5                  0x00000004U /*!< DMA Channel 5 */
-#if defined(DMA1_Channel6)
-#define LL_DMA_CHANNEL_6                  0x00000005U /*!< DMA Channel 6 */
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-#define LL_DMA_CHANNEL_7                  0x00000006U /*!< DMA Channel 7 */
-#endif /* DMA1_Channel7 */
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
-#endif /*USE_FULL_LL_DRIVER*/
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
-  * @{
-  */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MODE Transfer mode
-  * @{
-  */
-#define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
-#define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
-  * @{
-  */
-#define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
-#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
-  * @{
-  */
-#define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
-#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
-  * @{
-  */
-#define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
-#define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
-  * @{
-  */
-#define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
-#define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
-  * @{
-  */
-#define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
-#define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
-#define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
-#define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
-  * @{
-  */
-/**
-  * @brief  Write a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
-  * @{
-  */
-/**
-  * @brief  Convert DMAx_Channely into DMAx
-  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
-  * @retval DMAx
-  */
-#if defined(DMA2)
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)
-#else /* DMA1 */
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
-#endif /* DMA2 */
-
-/**
-  * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
-  * @param  __CHANNEL_INSTANCE__ DMAx_Channely
-  * @retval LL_DMA_CHANNEL_y
-  */
-#if defined(DMA2)
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#else /* DMA1 */
-#if   defined(DMA1_Channel7)
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#else
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- LL_DMA_CHANNEL_5)
-#endif /* DMA1_Channel8 */
-#endif /* DMA2 */
-
-/**
-  * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
-  * @param  __DMA_INSTANCE__ DMAx
-  * @param  __CHANNEL__ LL_DMA_CHANNEL_y
-  * @retval DMAx_Channely
-  */
-#if defined(DMA2)
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#else /* DMA1 */
-#if   defined(DMA1_Channel7)
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#else
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- DMA1_Channel5)
-#endif /* DMA1_Channel8 */
-#endif /* DMA2 */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Enable DMA channel.
-  * @rmtoll CCR          EN            LL_DMA_EnableChannel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
-}
-
-/**
-  * @brief  Disable DMA channel.
-  * @rmtoll CCR          EN            LL_DMA_DisableChannel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
-}
-
-/**
-  * @brief  Check if DMA channel is enabled or disabled.
-  * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                    DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure all parameters link to DMA transfer.
-  * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
-  *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
-  *         CCR          CIRC          LL_DMA_ConfigTransfer\n
-  *         CCR          PINC          LL_DMA_ConfigTransfer\n
-  *         CCR          MINC          LL_DMA_ConfigTransfer\n
-  *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
-  *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
-  *         CCR          PL            LL_DMA_ConfigTransfer
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
-  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-             DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
-             Configuration);
-}
-
-/**
-  * @brief  Set Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
-  *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-             DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
-}
-
-/**
-  * @brief  Get Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
-  *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                   DMA_CCR_DIR | DMA_CCR_MEM2MEM));
-}
-
-/**
-  * @brief  Set DMA mode circular or normal.
-  * @note The circular buffer mode cannot be used if the memory-to-memory
-  * data transfer is configured on the selected Channel.
-  * @rmtoll CCR          CIRC          LL_DMA_SetMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
-             Mode);
-}
-
-/**
-  * @brief  Get DMA mode circular or normal.
-  * @rmtoll CCR          CIRC          LL_DMA_GetMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                   DMA_CCR_CIRC));
-}
-
-/**
-  * @brief  Set Peripheral increment mode.
-  * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
-             PeriphOrM2MSrcIncMode);
-}
-
-/**
-  * @brief  Get Peripheral increment mode.
-  * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                   DMA_CCR_PINC));
-}
-
-/**
-  * @brief  Set Memory increment mode.
-  * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
-             MemoryOrM2MDstIncMode);
-}
-
-/**
-  * @brief  Get Memory increment mode.
-  * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                   DMA_CCR_MINC));
-}
-
-/**
-  * @brief  Set Peripheral size.
-  * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
-             PeriphOrM2MSrcDataSize);
-}
-
-/**
-  * @brief  Get Peripheral size.
-  * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                   DMA_CCR_PSIZE));
-}
-
-/**
-  * @brief  Set Memory size.
-  * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
-             MemoryOrM2MDstDataSize);
-}
-
-/**
-  * @brief  Get Memory size.
-  * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                   DMA_CCR_MSIZE));
-}
-
-/**
-  * @brief  Set Channel priority level.
-  * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Priority This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
-             Priority);
-}
-
-/**
-  * @brief  Get Channel priority level.
-  * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                   DMA_CCR_PL));
-}
-
-/**
-  * @brief  Set Number of data to transfer.
-  * @note   This action has no effect if
-  *         channel is enabled.
-  * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
-             DMA_CNDTR_NDT, NbData);
-}
-
-/**
-  * @brief  Get Number of data to transfer.
-  * @note   Once the channel is enabled, the return value indicate the
-  *         remaining bytes to be transmitted.
-  * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
-                   DMA_CNDTR_NDT));
-}
-
-/**
-  * @brief  Configure the Source and Destination addresses.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @note   Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
-  * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
-  *         CMAR         MA            LL_DMA_ConfigAddresses
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
-                                            uint32_t DstAddress, uint32_t Direction)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  /* Direction Memory to Periph */
-  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
-  {
-    WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress);
-    WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress);
-  }
-  /* Direction Periph to Memory and Memory to Memory */
-  else
-  {
-    WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
-    WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress);
-  }
-}
-
-/**
-  * @brief  Set the Memory address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Peripheral address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
-}
-
-/**
-  * @brief  Get Memory address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
-}
-
-/**
-  * @brief  Get Peripheral address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
-}
-
-/**
-  * @brief  Set the Memory to Memory Source address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Memory to Memory Destination address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
-}
-
-/**
-  * @brief  Get the Memory to Memory Source address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
-}
-
-/**
-  * @brief  Get the Memory to Memory Destination address.
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
-}
-
-/**
-  * @brief  Set DMA request for DMA Channels on DMAMUX Channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  Request This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX_REQ_ADC1
-  *         @arg @ref LL_DMAMUX_REQ_AES_IN
-  *         @arg @ref LL_DMAMUX_REQ_AES_OUT
-  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
-  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
-  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
-  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
-  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
-  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
-  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
-  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
-  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
-  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
-  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
-  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
-  *         @arg @ref LL_DMAMUX_REQ_USART1_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART1_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART2_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART2_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART3_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART3_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART4_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART4_TX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD2_RX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD2_TX
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
-{
-  uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
-  MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
-}
-
-/**
-  * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX_REQ_ADC1
-  *         @arg @ref LL_DMAMUX_REQ_AES_IN
-  *         @arg @ref LL_DMAMUX_REQ_AES_OUT
-  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
-  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
-  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
-  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
-  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
-  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
-  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
-  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
-  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
-  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
-  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
-  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
-  *         @arg @ref LL_DMAMUX_REQ_USART1_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART1_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART2_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART2_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART3_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART3_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART4_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART4_TX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD2_RX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD2_TX
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
-  return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Channel 1 global interrupt flag.
-  * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 2 global interrupt flag.
-  * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 3 global interrupt flag.
-  * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 4 global interrupt flag.
-  * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 5 global interrupt flag.
-  * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Get Channel 6 global interrupt flag.
-  * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
-}
-
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Get Channel 7 global interrupt flag.
-  * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
-}
-
-#endif /* DMA1_Channel7 */
-/**
-  * @brief  Get Channel 1 transfer complete flag.
-  * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 2 transfer complete flag.
-  * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 3 transfer complete flag.
-  * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 4 transfer complete flag.
-  * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 5 transfer complete flag.
-  * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Get Channel 6 transfer complete flag.
-  * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
-}
-
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Get Channel 7 transfer complete flag.
-  * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
-}
-
-#endif /* DMA1_Channel7 */
-/**
-  * @brief  Get Channel 1 half transfer flag.
-  * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 2 half transfer flag.
-  * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 3 half transfer flag.
-  * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 4 half transfer flag.
-  * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 5 half transfer flag.
-  * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Get Channel 6 half transfer flag.
-  * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
-}
-
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Get Channel 7 half transfer flag.
-  * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
-}
-
-#endif /* DMA1_Channel7 */
-/**
-  * @brief  Get Channel 1 transfer error flag.
-  * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 2 transfer error flag.
-  * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 3 transfer error flag.
-  * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 4 transfer error flag.
-  * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Channel 5 transfer error flag.
-  * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Get Channel 6 transfer error flag.
-  * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
-}
-
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Get Channel 7 transfer error flag.
-  * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
-{
-  return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
-}
-
-#endif /* DMA1_Channel7 */
-/**
-  * @brief  Clear Channel 1 global interrupt flag.
-  * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
-    Instead clear specific flags transfer complete, half transfer & transfer
-    error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
-    LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet.
-  * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
-}
-
-/**
-  * @brief  Clear Channel 2 global interrupt flag.
-  * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
-    Instead clear specific flags transfer complete, half transfer & transfer
-    error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
-    LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet.
-  * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
-}
-
-/**
-  * @brief  Clear Channel 3 global interrupt flag.
-  * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
-    Instead clear specific flags transfer complete, half transfer & transfer
-    error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
-    LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet.
-  * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
-}
-
-/**
-  * @brief  Clear Channel 4 global interrupt flag.
-  * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
-    Instead clear specific flags transfer complete, half transfer & transfer
-    error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
-    LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet.
-  * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
-}
-
-/**
-  * @brief  Clear Channel 5 global interrupt flag.
-  * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
-    Instead clear specific flags transfer complete, half transfer & transfer
-    error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
-    LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet.
-  * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Clear Channel 6 global interrupt flag.
-  * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
-    Instead clear specific flags transfer complete, half transfer & transfer
-    error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
-    LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet.
-  * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
-}
-
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Clear Channel 7 global interrupt flag.
-  * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
-    Instead clear specific flags transfer complete, half transfer & transfer
-    error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
-    LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet.
-  * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
-}
-
-#endif /* DMA1_Channel7 */
-/**
-  * @brief  Clear Channel 1  transfer complete flag.
-  * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
-}
-
-/**
-  * @brief  Clear Channel 2  transfer complete flag.
-  * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
-}
-
-/**
-  * @brief  Clear Channel 3  transfer complete flag.
-  * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
-}
-
-/**
-  * @brief  Clear Channel 4  transfer complete flag.
-  * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
-}
-
-/**
-  * @brief  Clear Channel 5  transfer complete flag.
-  * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Clear Channel 6  transfer complete flag.
-  * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
-}
-
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Clear Channel 7  transfer complete flag.
-  * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
-}
-
-#endif /* DMA1_Channel7 */
-/**
-  * @brief  Clear Channel 1  half transfer flag.
-  * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
-}
-
-/**
-  * @brief  Clear Channel 2  half transfer flag.
-  * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
-}
-
-/**
-  * @brief  Clear Channel 3  half transfer flag.
-  * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
-}
-
-/**
-  * @brief  Clear Channel 4  half transfer flag.
-  * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
-}
-
-/**
-  * @brief  Clear Channel 5  half transfer flag.
-  * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Clear Channel 6  half transfer flag.
-  * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
-}
-
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Clear Channel 7  half transfer flag.
-  * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
-}
-
-#endif /* DMA1_Channel7 */
-/**
-  * @brief  Clear Channel 1 transfer error flag.
-  * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
-}
-
-/**
-  * @brief  Clear Channel 2 transfer error flag.
-  * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
-}
-
-/**
-  * @brief  Clear Channel 3 transfer error flag.
-  * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
-}
-
-/**
-  * @brief  Clear Channel 4 transfer error flag.
-  * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
-}
-
-/**
-  * @brief  Clear Channel 5 transfer error flag.
-  * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
-}
-
-#if defined(DMA1_Channel6)
-/**
-  * @brief  Clear Channel 6 transfer error flag.
-  * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
-}
-
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-/**
-  * @brief  Clear Channel 7 transfer error flag.
-  * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
-}
-
-#endif /* DMA1_Channel7 */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
-  * @{
-  */
-/**
-  * @brief  Enable Transfer complete interrupt.
-  * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
-}
-
-/**
-  * @brief  Enable Half transfer interrupt.
-  * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
-}
-
-/**
-  * @brief  Enable Transfer error interrupt.
-  * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
-}
-
-/**
-  * @brief  Disable Transfer complete interrupt.
-  * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
-}
-
-/**
-  * @brief  Disable Half transfer interrupt.
-  * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
-}
-
-/**
-  * @brief  Disable Transfer error interrupt.
-  * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
-}
-
-/**
-  * @brief  Check if Transfer complete Interrupt is enabled.
-  * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                    DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Half transfer Interrupt is enabled.
-  * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                    DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Transfer error Interrupt is enabled.
-  * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  uint32_t dma_base_addr = (uint32_t)DMAx;
-  return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
-                    DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
-ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMA1 || DMA2 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h

@@ -1,1828 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_dmamux.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMAMUX LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_DMAMUX_H
-#define STM32G0xx_LL_DMAMUX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMAMUX1)
-
-/** @defgroup DMAMUX_LL DMAMUX
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
-  * @{
-  */
-/* Define used to get DMAMUX CCR register size */
-#define DMAMUX_CCR_SIZE                   0x00000004UL
-
-/* Define used to get DMAMUX RGCR register size */
-#define DMAMUX_RGCR_SIZE                  0x00000004UL
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
-  * @{
-  */
-/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function
-  * @{
-  */
-#define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
-#define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
-#define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
-#define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
-#define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
-#if defined(DMAMUX1_Channel5)
-#define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
-#endif /* DMAMUX1_Channel5 */
-#if defined(DMAMUX1_Channel6)
-#define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
-#endif /* DMAMUX1_Channel6 */
-#if defined(DMA2)
-#define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
-#define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
-#define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
-#define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
-#define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
-#endif /* DMA2 */
-#define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function
-  * @{
-  */
-#define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0  */
-#define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1  */
-#define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2  */
-#define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3  */
-#define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4  */
-#if defined(DMAMUX1_Channel5)
-#define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5  */
-#endif /* DMAMUX1_Channel5 */
-#if defined(DMAMUX1_Channel6)
-#define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6  */
-#endif /* DMAMUX1_Channel6 */
-#if defined(DMA2)
-#define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7  */
-#define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8  */
-#define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9  */
-#define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10 */
-#define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11 */
-#endif /* DMA2 */
-#define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */
-#define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions
-  * @{
-  */
-#define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt */
-#define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
-  * @{
-  */
-#define LL_DMAMUX_REQ_MEM2MEM             0x00000000U  /*!< memory to memory transfer  */
-#define LL_DMAMUX_REQ_GENERATOR0          0x00000001U  /*!< DMAMUX request generator 0 */
-#define LL_DMAMUX_REQ_GENERATOR1          0x00000002U  /*!< DMAMUX request generator 1 */
-#define LL_DMAMUX_REQ_GENERATOR2          0x00000003U  /*!< DMAMUX request generator 2 */
-#define LL_DMAMUX_REQ_GENERATOR3          0x00000004U  /*!< DMAMUX request generator 3 */
-#define LL_DMAMUX_REQ_ADC1                0x00000005U  /*!< DMAMUX ADC1 request        */
-#if defined(AES)
-#define LL_DMAMUX_REQ_AES_IN              0x00000006U  /*!< DMAMUX AES_IN request      */
-#define LL_DMAMUX_REQ_AES_OUT             0x00000007U  /*!< DMAMUX AES_OUT request     */
-#endif /* AES */
-#if defined(DAC1)
-#define LL_DMAMUX_REQ_DAC1_CH1            0x00000008U  /*!< DMAMUX DAC_CH1 request     */
-#define LL_DMAMUX_REQ_DAC1_CH2            0x00000009U  /*!< DMAMUX DAC_CH2 request     */
-#endif /* DAC1 */
-#define LL_DMAMUX_REQ_I2C1_RX             0x0000000AU  /*!< DMAMUX I2C1 RX request     */
-#define LL_DMAMUX_REQ_I2C1_TX             0x0000000BU  /*!< DMAMUX I2C1 TX request     */
-#define LL_DMAMUX_REQ_I2C2_RX             0x0000000CU  /*!< DMAMUX I2C2 RX request     */
-#define LL_DMAMUX_REQ_I2C2_TX             0x0000000DU  /*!< DMAMUX I2C2 TX request     */
-#if defined(LPUART1)
-#define LL_DMAMUX_REQ_LPUART1_RX          0x0000000EU  /*!< DMAMUX LPUART1 RX request  */
-#define LL_DMAMUX_REQ_LPUART1_TX          0x0000000FU  /*!< DMAMUX LPUART1 TX request  */
-#endif /* LPUART1 */
-#define LL_DMAMUX_REQ_SPI1_RX             0x00000010U  /*!< DMAMUX SPI1 RX request     */
-#define LL_DMAMUX_REQ_SPI1_TX             0x00000011U  /*!< DMAMUX SPI1 TX request     */
-#define LL_DMAMUX_REQ_SPI2_RX             0x00000012U  /*!< DMAMUX SPI2 RX request     */
-#define LL_DMAMUX_REQ_SPI2_TX             0x00000013U  /*!< DMAMUX SPI2 TX request     */
-#define LL_DMAMUX_REQ_TIM1_CH1            0x00000014U  /*!< DMAMUX TIM1 CH1 request    */
-#define LL_DMAMUX_REQ_TIM1_CH2            0x00000015U  /*!< DMAMUX TIM1 CH2 request    */
-#define LL_DMAMUX_REQ_TIM1_CH3            0x00000016U  /*!< DMAMUX TIM1 CH3 request    */
-#define LL_DMAMUX_REQ_TIM1_CH4            0x00000017U  /*!< DMAMUX TIM1 CH4 request    */
-#define LL_DMAMUX_REQ_TIM1_TRIG_COM       0x00000018U  /*!< DMAMUX TIM1 TRIG COM request */
-#define LL_DMAMUX_REQ_TIM1_UP             0x00000019U  /*!< DMAMUX TIM1 UP request     */
-#if defined(TIM2)
-#define LL_DMAMUX_REQ_TIM2_CH1            0x0000001AU  /*!< DMAMUX TIM2 CH1 request    */
-#define LL_DMAMUX_REQ_TIM2_CH2            0x0000001BU  /*!< DMAMUX TIM2 CH2 request    */
-#define LL_DMAMUX_REQ_TIM2_CH3            0x0000001CU  /*!< DMAMUX TIM2 CH3 request    */
-#define LL_DMAMUX_REQ_TIM2_CH4            0x0000001DU  /*!< DMAMUX TIM2 CH4 request    */
-#define LL_DMAMUX_REQ_TIM2_TRIG           0x0000001EU  /*!< DMAMUX TIM2 TRIG request   */
-#define LL_DMAMUX_REQ_TIM2_UP             0x0000001FU  /*!< DMAMUX TIM2 UP request     */
-#endif /* TIM2 */
-#define LL_DMAMUX_REQ_TIM3_CH1            0x00000020U  /*!< DMAMUX TIM3 CH1 request    */
-#define LL_DMAMUX_REQ_TIM3_CH2            0x00000021U  /*!< DMAMUX TIM3 CH2 request    */
-#define LL_DMAMUX_REQ_TIM3_CH3            0x00000022U  /*!< DMAMUX TIM3 CH3 request    */
-#define LL_DMAMUX_REQ_TIM3_CH4            0x00000023U  /*!< DMAMUX TIM3 CH4 request    */
-#define LL_DMAMUX_REQ_TIM3_TRIG           0x00000024U  /*!< DMAMUX TIM3 TRIG request   */
-#define LL_DMAMUX_REQ_TIM3_UP             0x00000025U  /*!< DMAMUX TIM3 UP request     */
-#if defined(TIM6)
-#define LL_DMAMUX_REQ_TIM6_UP             0x00000026U  /*!< DMAMUX TIM6 UP request     */
-#endif /* TIM6 */
-#if defined(TIM7)
-#define LL_DMAMUX_REQ_TIM7_UP             0x00000027U  /*!< DMAMUX TIM7 UP request     */
-#endif /* TIM7 */
-#if defined(TIM15)
-#define LL_DMAMUX_REQ_TIM15_CH1           0x00000028U  /*!< DMAMUX TIM15 CH1 request   */
-#define LL_DMAMUX_REQ_TIM15_CH2           0x00000029U  /*!< DMAMUX TIM15 CH2 request   */
-#define LL_DMAMUX_REQ_TIM15_TRIG_COM      0x0000002AU  /*!< DMAMUX TIM15 TRIG COM request */
-#define LL_DMAMUX_REQ_TIM15_UP            0x0000002BU  /*!< DMAMUX TIM15 UP request    */
-#endif /* TIM15 */
-#define LL_DMAMUX_REQ_TIM16_CH1           0x0000002CU  /*!< DMAMUX TIM16 CH1 request   */
-#define LL_DMAMUX_REQ_TIM16_COM           0x0000002DU  /*!< DMAMUX TIM16 COM request   */
-#define LL_DMAMUX_REQ_TIM16_UP            0x0000002EU  /*!< DMAMUX TIM16 UP request    */
-#define LL_DMAMUX_REQ_TIM17_CH1           0x0000002FU  /*!< DMAMUX TIM17 CH1 request   */
-#define LL_DMAMUX_REQ_TIM17_COM           0x00000030U  /*!< DMAMUX TIM17 COM request   */
-#define LL_DMAMUX_REQ_TIM17_UP            0x00000031U  /*!< DMAMUX TIM17 UP request    */
-#define LL_DMAMUX_REQ_USART1_RX           0x00000032U  /*!< DMAMUX USART1 RX request  */
-#define LL_DMAMUX_REQ_USART1_TX           0x00000033U  /*!< DMAMUX USART1 TX request  */
-#define LL_DMAMUX_REQ_USART2_RX           0x00000034U  /*!< DMAMUX USART2 RX request  */
-#define LL_DMAMUX_REQ_USART2_TX           0x00000035U  /*!< DMAMUX USART2 TX request  */
-#if defined(USART3)
-#define LL_DMAMUX_REQ_USART3_RX           0x00000036U  /*!< DMAMUX USART3 RX request  */
-#define LL_DMAMUX_REQ_USART3_TX           0x00000037U  /*!< DMAMUX USART3 TX request  */
-#endif /* USART3 */
-#if defined(USART4)
-#define LL_DMAMUX_REQ_USART4_RX           0x00000038U  /*!< DMAMUX USART4 RX request  */
-#define LL_DMAMUX_REQ_USART4_TX           0x00000039U  /*!< DMAMUX USART4 TX request  */
-#endif /* USART4 */
-#if defined(UCPD1)
-#define LL_DMAMUX_REQ_UCPD1_RX            0x0000003AU  /*!< DMAMUX UCPD1 RX request  */
-#define LL_DMAMUX_REQ_UCPD1_TX            0x0000003BU  /*!< DMAMUX UCPD1 TX request  */
-#endif /* UCPD1 */
-#if defined(UCPD2)
-#define LL_DMAMUX_REQ_UCPD2_RX            0x0000003CU  /*!< DMAMUX UCPD2 RX request  */
-#define LL_DMAMUX_REQ_UCPD2_TX            0x0000003DU  /*!< DMAMUX UCPD2 TX request  */
-#endif /* UCPD2 */
-
-#if defined(I2C3)
-#define LL_DMAMUX_REQ_I2C3_RX             0x0000003EU  /*!< DMAMUX I2C3 RX request  */
-#define LL_DMAMUX_REQ_I2C3_TX             0x0000003FU  /*!< DMAMUX I2C3 TX request  */
-#endif /* I2C3 */
-
-#if defined(LPUART2)
-#define LL_DMAMUX_REQ_LPUART2_RX          0x00000040U  /*!< DMAMUX LPUART2 RX request  */
-#define LL_DMAMUX_REQ_LPUART2_TX          0x00000041U  /*!< DMAMUX LPUART2 TX request  */
-#endif /* LPUART2 */
-
-#if defined(SPI3)
-#define LL_DMAMUX_REQ_SPI3_RX             0x00000042U  /*!< DMAMUX SPI3 RX request     */
-#define LL_DMAMUX_REQ_SPI3_TX             0x00000043U  /*!< DMAMUX SPI3 TX request     */
-#endif /* SPI3 */
-
-#if defined(TIM4)
-#define LL_DMAMUX_REQ_TIM4_CH1            0x00000044U  /*!< DMAMUX TIM4 CH1 request    */
-#define LL_DMAMUX_REQ_TIM4_CH2            0x00000045U  /*!< DMAMUX TIM4 CH2 request    */
-#define LL_DMAMUX_REQ_TIM4_CH3            0x00000046U  /*!< DMAMUX TIM4 CH3 request    */
-#define LL_DMAMUX_REQ_TIM4_CH4            0x00000047U  /*!< DMAMUX TIM4 CH4 request    */
-#define LL_DMAMUX_REQ_TIM4_TRIG           0x00000048U  /*!< DMAMUX TIM4 TRIG request   */
-#define LL_DMAMUX_REQ_TIM4_UP             0x00000049U  /*!< DMAMUX TIM4 UP request     */
-#endif /* TIM4 */
-
-#if defined(USART5)
-#define LL_DMAMUX_REQ_USART5_RX           0x0000004AU  /*!< DMAMUX USART5 RX request  */
-#define LL_DMAMUX_REQ_USART5_TX           0x0000004BU  /*!< DMAMUX USART5 TX request  */
-#endif /* USART5 */
-
-#if defined(USART6)
-#define LL_DMAMUX_REQ_USART6_RX           0x0000004CU  /*!< DMAMUX USART6 RX request  */
-#define LL_DMAMUX_REQ_USART6_TX           0x0000004DU  /*!< DMAMUX USART6 TX request  */
-#endif /* USART6 */
-
-#if defined(STM32G0C1xx)||defined(STM32G0B1xx)
-#define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_USART6_TX
-#elif defined(STM32G0B0xx)
-#define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_USART4_TX
-#elif defined(STM32G081xx)||defined(STM32G071xx)
-#define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_UCPD2_TX
-#elif defined(STM32G070xx)
-#define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_USART4_TX
-#else
-#define LL_DMAMUX_MAX_REQ                 LL_DMAMUX_REQ_USART2_TX
-#endif /* STM32G0C1xx || STM32G0B1xx */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
-  * @{
-  */
-#define LL_DMAMUX_CHANNEL_0               0x00000000U               /*!< DMAMUX Channel 0 connected to DMA1 Channel 1  */
-#define LL_DMAMUX_CHANNEL_1               0x00000001U               /*!< DMAMUX Channel 1 connected to DMA1 Channel 2  */
-#define LL_DMAMUX_CHANNEL_2               0x00000002U               /*!< DMAMUX Channel 2 connected to DMA1 Channel 3  */
-#define LL_DMAMUX_CHANNEL_3               0x00000003U               /*!< DMAMUX Channel 3 connected to DMA1 Channel 4  */
-#define LL_DMAMUX_CHANNEL_4               0x00000004U               /*!< DMAMUX Channel 4 connected to DMA1 Channel 5  */
-#if defined(DMAMUX1_Channel5)
-#define LL_DMAMUX_CHANNEL_5               0x00000005U               /*!< DMAMUX Channel 5 connected to DMA1 Channel 6  */
-#endif /* DMAMUX1_Channel5 */
-#if defined(DMAMUX1_Channel6)
-#define LL_DMAMUX_CHANNEL_6               0x00000006U               /*!< DMAMUX Channel 6 connected to DMA1 Channel 7  */
-#endif /* DMAMUX1_Channel6 */
-#if defined(DMA2)
-#define LL_DMAMUX_CHANNEL_7               0x00000007U               /*!< DMAMUX Channel 7 connected to DMA2 Channel 1  */
-#define LL_DMAMUX_CHANNEL_8               0x00000008U               /*!< DMAMUX Channel 8 connected to DMA2 Channel 2  */
-#define LL_DMAMUX_CHANNEL_9               0x00000009U               /*!< DMAMUX Channel 9 connected to DMA2 Channel 3  */
-#define LL_DMAMUX_CHANNEL_10              0x0000000AU               /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */
-#define LL_DMAMUX_CHANNEL_11              0x0000000BU               /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */
-#endif /* DMA2 */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
-  * @{
-  */
-#define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked   */
-#define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge */
-#define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge */
-#define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
-  * @{
-  */
-#define LL_DMAMUX_SYNC_EXTI_LINE0         0x00000000U                                                                                     /*!< Synchronization signal from EXTI Line0  */
-#define LL_DMAMUX_SYNC_EXTI_LINE1         DMAMUX_CxCR_SYNC_ID_0                                                                           /*!< Synchronization signal from EXTI Line1  */
-#define LL_DMAMUX_SYNC_EXTI_LINE2         DMAMUX_CxCR_SYNC_ID_1                                                                           /*!< Synchronization signal from EXTI Line2  */
-#define LL_DMAMUX_SYNC_EXTI_LINE3         (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line3  */
-#define LL_DMAMUX_SYNC_EXTI_LINE4         DMAMUX_CxCR_SYNC_ID_2                                                                           /*!< Synchronization signal from EXTI Line4  */
-#define LL_DMAMUX_SYNC_EXTI_LINE5         (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line5  */
-#define LL_DMAMUX_SYNC_EXTI_LINE6         (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line6  */
-#define LL_DMAMUX_SYNC_EXTI_LINE7         (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line7  */
-#define LL_DMAMUX_SYNC_EXTI_LINE8         DMAMUX_CxCR_SYNC_ID_3                                                                           /*!< Synchronization signal from EXTI Line8  */
-#define LL_DMAMUX_SYNC_EXTI_LINE9         (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from EXTI Line9  */
-#define LL_DMAMUX_SYNC_EXTI_LINE10        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from EXTI Line10  */
-#define LL_DMAMUX_SYNC_EXTI_LINE11        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line11  */
-#define LL_DMAMUX_SYNC_EXTI_LINE12        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2)                                                 /*!< Synchronization signal from EXTI Line12  */
-#define LL_DMAMUX_SYNC_EXTI_LINE13        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from EXTI Line1 3 */
-#define LL_DMAMUX_SYNC_EXTI_LINE14        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                         /*!< Synchronization signal from EXTI Line1 4 */
-#define LL_DMAMUX_SYNC_EXTI_LINE15        (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 5 */
-#define LL_DMAMUX_SYNC_DMAMUX_CH0         DMAMUX_CxCR_SYNC_ID_4                                                                           /*!< Synchronization signal from DMAMUX channel0 Event */
-#define LL_DMAMUX_SYNC_DMAMUX_CH1         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0)                                                 /*!< Synchronization signal from DMAMUX channel1 Event */
-#define LL_DMAMUX_SYNC_DMAMUX_CH2         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1)                                                 /*!< Synchronization signal from DMAMUX channel2 Event */
-#define LL_DMAMUX_SYNC_DMAMUX_CH3         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from DMAMUX channel3 Event */
-#if defined(LPTIM1)
-#define LL_DMAMUX_SYNC_LPTIM1_OUT         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2)                                                 /*!< Synchronization signal from LPTIM1 Output */
-#endif /* LPTIM1 */
-#if defined(LPTIM2)
-#define LL_DMAMUX_SYNC_LPTIM2_OUT         (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0)                         /*!< Synchronization signal from LPTIM2 Output */
-#endif /* LPTIM2 */
-#define LL_DMAMUX_SYNC_TIM14_OC           (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1)                         /*!< Synchronization signal from TIM14 OC */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
-  * @{
-  */
-#define LL_DMAMUX_REQ_GEN_0               0x00000000U
-#define LL_DMAMUX_REQ_GEN_1               0x00000001U
-#define LL_DMAMUX_REQ_GEN_2               0x00000002U
-#define LL_DMAMUX_REQ_GEN_3               0x00000003U
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
-  * @{
-  */
-#define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation */
-#define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge */
-#define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge */
-#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
-  * @{
-  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE0      0x00000000U                                                                                     /*!< Request signal generation from EXTI Line0  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE1      DMAMUX_RGxCR_SIG_ID_0                                                                           /*!< Request signal generation from EXTI Line1  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE2      DMAMUX_RGxCR_SIG_ID_1                                                                           /*!< Request signal generation from EXTI Line2  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE3      (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0)                                                  /*!< Request signal generation from EXTI Line3  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE4      DMAMUX_RGxCR_SIG_ID_2                                                                           /*!< Request signal generation from EXTI Line4  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE5      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line5  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE6      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line6  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE7      (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line7  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE8      DMAMUX_RGxCR_SIG_ID_3                                                                           /*!< Request signal generation from EXTI Line8  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE9      (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from EXTI Line9  */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE10     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from EXTI Line10 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE11     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line11 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE12     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2)                                                 /*!< Request signal generation from EXTI Line12 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE13     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from EXTI Line13 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE14     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                         /*!< Request signal generation from EXTI Line14 */
-#define LL_DMAMUX_REQ_GEN_EXTI_LINE15     (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
-#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0      DMAMUX_RGxCR_SIG_ID_4                                                                           /*!< Request signal generation from DMAMUX channel0 Event */
-#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0)                                                 /*!< Request signal generation from DMAMUX channel1 Event */
-#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1)                                                 /*!< Request signal generation from DMAMUX channel2 Event */
-#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from DMAMUX channel3 Event */
-#if defined(LPTIM1)
-#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2)                                                 /*!< Request signal generation from LPTIM1 Output */
-#endif /* LPTIM1 */
-#if defined(LPTIM2)
-#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT      (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0)                         /*!< Request signal generation from LPTIM2 Output */
-#endif /* LPTIM2 */
-#define LL_DMAMUX_REQ_GEN_TIM14_OC        (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1)                         /*!< Request signal generation from TIM14 OC */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
-  * @{
-  */
-
-/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
-  * @{
-  */
-/**
-  * @brief  Write a value in DMAMUX register
-  * @param  __INSTANCE__ DMAMUX Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in DMAMUX register
-  * @param  __INSTANCE__ DMAMUX Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
- * @{
- */
-
-/** @defgroup DMAMUX_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Set DMAMUX request ID for DMAMUX Channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @param  Request This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX_REQ_ADC1
-  *         @arg @ref LL_DMAMUX_REQ_AES_IN
-  *         @arg @ref LL_DMAMUX_REQ_AES_OUT
-  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
-  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
-  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
-  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
-  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
-  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
-  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
-  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
-  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
-  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
-  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
-  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
-  *         @arg @ref LL_DMAMUX_REQ_USART1_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART1_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART2_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART2_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART3_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART3_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART4_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART4_TX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD2_RX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD2_TX
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
-{
-  (void)(DMAMUXx);
-  MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
-}
-
-/**
-  * @brief  Get DMAMUX request ID for DMAMUX Channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2
-  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3
-  *         @arg @ref LL_DMAMUX_REQ_ADC1
-  *         @arg @ref LL_DMAMUX_REQ_AES_IN
-  *         @arg @ref LL_DMAMUX_REQ_AES_OUT
-  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1
-  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2
-  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX
-  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX
-  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX
-  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX
-  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX
-  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX
-  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX
-  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX
-  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX
-  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_TRIG
-  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
-  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH2
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_COM
-  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP
-  *         @arg @ref LL_DMAMUX_REQ_USART1_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART1_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART2_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART2_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART3_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART3_TX
-  *         @arg @ref LL_DMAMUX_REQ_USART4_RX
-  *         @arg @ref LL_DMAMUX_REQ_USART4_TX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD1_RX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD1_TX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD2_RX
-  *         @arg @ref LL_DMAMUX_REQ_UCPD2_TX
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
-}
-
-/**
-  * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
-{
-  (void)(DMAMUXx);
-  MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
-}
-
-/**
-  * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval Between Min_Data = 1 and Max_Data = 32
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
-}
-
-/**
-  * @brief  Set the polarity of the signal on which the DMA request is synchronized.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
-  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
-  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
-  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
-{
-  (void)(DMAMUXx);
-  MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
-}
-
-/**
-  * @brief  Get the polarity of the signal on which the DMA request is synchronized.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT
-  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING
-  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING
-  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
-}
-
-/**
-  * @brief  Enable the Event Generation on DMAMUX channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
-}
-
-/**
-  * @brief  Disable the Event Generation on DMAMUX channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
-}
-
-/**
-  * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the synchronization mode.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
-}
-
-/**
-  * @brief  Disable the synchronization mode.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
-}
-
-/**
-  * @brief  Check if the synchronization mode is enabled or disabled.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @param  SyncID This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
-  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
-  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
-  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
-  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
-  *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
-  *         @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX_SYNC_TIM14_OC
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
-{
-  (void)(DMAMUXx);
-  MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
-}
-
-/**
-  * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
-  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
-  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
-  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
-  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
-  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
-  *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
-  *         @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX_SYNC_TIM14_OC
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
-}
-
-/**
-  * @brief  Enable the Request Generator.
-  * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  (void)(DMAMUXx);
-  SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
-}
-
-/**
-  * @brief  Disable the Request Generator.
-  * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  (void)(DMAMUXx);
-  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
-}
-
-/**
-  * @brief  Check if the Request Generator is enabled or disabled.
-  * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the polarity of the signal on which the DMA request is generated.
-  * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
-{
-  (void)(DMAMUXx);
-  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
-}
-
-/**
-  * @brief  Get the polarity of the signal on which the DMA request is generated.
-  * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
-  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  (void)(DMAMUXx);
-  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
-}
-
-/**
-  * @brief  Set the number of DMA request that will be autorized after a generation event.
-  * @note   This field can only be written when Generator is disabled.
-  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
-{
-  (void)(DMAMUXx);
-  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
-}
-
-/**
-  * @brief  Get the number of DMA request that will be autorized after a generation event.
-  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval Between Min_Data = 1 and Max_Data = 32
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  (void)(DMAMUXx);
-  return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
-}
-
-/**
-  * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
-  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @param  RequestSignalID This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
-  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
-  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
-{
-  (void)(DMAMUXx);
-  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
-}
-
-/**
-  * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
-  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
-  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
-  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
-  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
-  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT
-  *         @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  (void)(DMAMUXx);
-  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 0.
-  * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 1.
-  * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 2.
-  * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 3.
-  * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 4.
-  * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
-}
-
-#if defined(DMAMUX1_Channel5)
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 5.
-  * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
-}
-
-#endif /* DMAMUX1_Channel5 */
-#if defined(DMAMUX1_Channel6)
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 6.
-  * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
-}
-
-#endif /* DMAMUX1_Channel6 */
-#if defined(DMAMUX1_Channel7)
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 7.
-  * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
-}
-
-#endif /* DMAMUX1_Channel7 */
-#if defined(DMAMUX1_Channel8)
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 8.
-  * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
-}
-
-#endif /* DMAMUX1_Channel8 */
-#if defined(DMAMUX1_Channel9)
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 9.
-  * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
-}
-
-#endif /* DMAMUX1_Channel9 */
-#if defined(DMAMUX1_Channel10)
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 10.
-  * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
-}
-
-#endif /* DMAMUX1_Channel10 */
-#if defined(DMAMUX1_Channel11)
-/**
-  * @brief  Get Synchronization Event Overrun Flag Channel 11.
-  * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
-}
-
-#endif /* DMAMUX1_Channel11 */
-/**
-  * @brief  Get Request Generator 0 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 1 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 2 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Request Generator 3 Trigger Event Overrun Flag.
-  * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 0.
-  * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 1.
-  * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 2.
-  * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 3.
-  * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
-}
-
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 4.
-  * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
-}
-
-#if defined(DMAMUX1_Channel5)
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 5.
-  * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
-}
-
-#endif /* DMAMUX1_Channel5 */
-#if defined(DMAMUX1_Channel6)
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 6.
-  * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
-}
-
-#endif /* DMAMUX1_Channel6 */
-#if defined(DMAMUX1_Channel7)
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 7.
-  * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
-}
-
-#endif /* DMAMUX1_Channel7 */
-#if defined(DMAMUX1_Channel8)
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 8.
-  * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
-}
-
-#endif /* DMAMUX1_Channel8 */
-#if defined(DMAMUX1_Channel9)
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 9.
-  * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
-}
-
-#endif /* DMAMUX1_Channel9 */
-#if defined(DMAMUX1_Channel10)
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 10.
-  * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
-}
-
-#endif /* DMAMUX1_Channel10 */
-#if defined(DMAMUX1_Channel11)
-/**
-  * @brief  Clear Synchronization Event Overrun Flag Channel 11.
-  * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
-}
-
-#endif /* DMAMUX1_Channel11 */
-/**
-  * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
-}
-
-/**
-  * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
-}
-
-/**
-  * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
-}
-
-/**
-  * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.
-  * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3
-  * @param  DMAMUXx DMAMUXx DMAMUXx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
-{
-  (void)(DMAMUXx);
-  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
-}
-
-/**
-  * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
-}
-
-/**
-  * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
-  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
-  *         DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****).
-  * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_CHANNEL_0
-  *         @arg @ref LL_DMAMUX_CHANNEL_1
-  *         @arg @ref LL_DMAMUX_CHANNEL_2
-  *         @arg @ref LL_DMAMUX_CHANNEL_3
-  *         @arg @ref LL_DMAMUX_CHANNEL_4
-  *         @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****)
-  *         @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****)
-  *
-  *         @arg All the next values are only available on chip which support DMA2:
-  *         @arg @ref LL_DMAMUX_CHANNEL_7
-  *         @arg @ref LL_DMAMUX_CHANNEL_8
-  *         @arg @ref LL_DMAMUX_CHANNEL_9
-  *         @arg @ref LL_DMAMUX_CHANNEL_10
-  *         @arg @ref LL_DMAMUX_CHANNEL_11
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
-{
-  (void)(DMAMUXx);
-  return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
-  * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  (void)(DMAMUXx);
-  SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
-}
-
-/**
-  * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
-  * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  (void)(DMAMUXx);
-  CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE);
-}
-
-/**
-  * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
-  * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO
-  * @param  DMAMUXx DMAMUXx Instance
-  * @param  RequestGenChannel This parameter can be one of the following values:
-  *         @arg @ref LL_DMAMUX_REQ_GEN_0
-  *         @arg @ref LL_DMAMUX_REQ_GEN_1
-  *         @arg @ref LL_DMAMUX_REQ_GEN_2
-  *         @arg @ref LL_DMAMUX_REQ_GEN_3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
-{
-  (void)(DMAMUXx);
-  return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMAMUX1 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_DMAMUX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_exti.h

@@ -1,1559 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_exti.h
-  * @author  MCD Application Team
-  * @brief   Header file of EXTI LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_EXTI_H
-#define STM32G0xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-#define LL_EXTI_REGISTER_PINPOS_SHFT        16u   /*!< Define used to shift pin position in EXTICR register */
-
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
-  * @{
-  */
-typedef struct
-{
-
-  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
-                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
-                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
-                                     This parameter can be set either to ENABLE or DISABLE */
-
-  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
-  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
-  * @{
-  */
-#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */
-#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */
-#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */
-#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */
-#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */
-#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */
-#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */
-#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */
-#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */
-#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */
-#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */
-#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */
-#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */
-#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */
-#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */
-#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */
-#if defined(EXTI_IMR1_IM16)
-#define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */
-#endif /* EXTI_IMR1_IM16 */
-#if defined(EXTI_IMR1_IM17)
-#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */
-#endif /* EXTI_IMR1_IM17 */
-#if defined(EXTI_IMR1_IM18)
-#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */
-#endif /* EXTI_IMR1_IM18 */
-#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */
-#if defined(EXTI_IMR1_IM20)
-#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */
-#endif /* EXTI_IMR1_IM20 */ 
-#if defined(EXTI_IMR1_IM21)
-#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */
-#endif /* EXTI_IMR1_IM21 */
-#if defined(EXTI_IMR1_IM22)
-#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */
-#endif /* EXTI_IMR1_IM22 */
-#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */
-#if defined(EXTI_IMR1_IM24)
-#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */
-#endif /* EXTI_IMR1_IM24 */
-#if defined(EXTI_IMR1_IM25)
-#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */
-#endif /* EXTI_IMR1_IM25 */
-#if defined(EXTI_IMR1_IM26)
-#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */
-#endif /* EXTI_IMR1_IM26 */
-#if defined(EXTI_IMR1_IM27)
-#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */
-#endif /* EXTI_IMR1_IM27 */
-#if defined(EXTI_IMR1_IM28)
-#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */
-#endif /* EXTI_IMR1_IM28 */
-#if defined(EXTI_IMR1_IM29)
-#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */
-#endif /* EXTI_IMR1_IM29 */
-#if defined(EXTI_IMR1_IM30)
-#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */
-#endif /* EXTI_IMR1_IM30 */
-#if defined(EXTI_IMR1_IM31)
-#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */
-#endif /* EXTI_IMR1_IM31 */
-#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/
-
-#if defined(EXTI_IMR2_IM32)
-#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */
-#endif /* EXTI_IMR2_IM32 */
-#if defined(EXTI_IMR2_IM33)
-#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */
-#endif /* EXTI_IMR2_IM33 */
-#if defined(EXTI_IMR2_IM34)
-#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */
-#endif /* EXTI_IMR2_IM34 */
-#if defined(EXTI_IMR2_IM35)
-#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */
-#endif /* EXTI_IMR2_IM35 */
-#if defined(EXTI_IMR2_IM36)
-#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */
-#endif /* EXTI_IMR2_IM36 */
-#if defined(EXTI_IMR2_IM32) || defined(EXTI_IMR2_IM33) || defined(EXTI_IMR2_IM34) || defined(EXTI_IMR2_IM35) || defined(EXTI_IMR2_IM36)
-#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/
-#endif /* EXTI_IMR2_IM32 || EXTI_IMR2_IM33 || EXTI_IMR2_IM34 || EXTI_IMR2_IM35 || EXTI_IMR2_IM36 */
-
-#define LL_EXTI_LINE_ALL               0xFFFFFFFFU             /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE              0x00000000U             /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup EXTI_LL_EC_CONFIG_PORT EXTI CONFIG PORT
-  * @{
-  */
-#define LL_EXTI_CONFIG_PORTA               0U                                          /*!< EXTI PORT A */
-#define LL_EXTI_CONFIG_PORTB               EXTI_EXTICR1_EXTI0_0                        /*!< EXTI PORT B */
-#define LL_EXTI_CONFIG_PORTC               EXTI_EXTICR1_EXTI0_1                        /*!< EXTI PORT C */
-#if defined(GPIOD_BASE)
-#define LL_EXTI_CONFIG_PORTD               (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */
-#endif /*GPIOD_BASE*/
-#if defined(GPIOE_BASE)
-#define LL_EXTI_CONFIG_PORTE               EXTI_EXTICR1_EXTI0_2                        /*!< EXTI PORT E */
-#endif /*GPIOE_BASE*/
-#define LL_EXTI_CONFIG_PORTF               (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EC_CONFIG_LINE EXTI CONFIG LINE
-  * @{
-  */
-#define LL_EXTI_CONFIG_LINE0               ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
-#define LL_EXTI_CONFIG_LINE1               ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
-#define LL_EXTI_CONFIG_LINE2               ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)  /*!< EXTI_POSITION_16 | EXTICR[0] */
-#define LL_EXTI_CONFIG_LINE3               ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)  /*!< EXTI_POSITION_24 | EXTICR[0] */
-#define LL_EXTI_CONFIG_LINE4               ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
-#define LL_EXTI_CONFIG_LINE5               ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
-#define LL_EXTI_CONFIG_LINE6               ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)  /*!< EXTI_POSITION_16 | EXTICR[1] */
-#define LL_EXTI_CONFIG_LINE7               ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)  /*!< EXTI_POSITION_24 | EXTICR[1] */
-#define LL_EXTI_CONFIG_LINE8               ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
-#define LL_EXTI_CONFIG_LINE9               ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
-#define LL_EXTI_CONFIG_LINE10              ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)  /*!< EXTI_POSITION_16 | EXTICR[2] */
-#define LL_EXTI_CONFIG_LINE11              ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)  /*!< EXTI_POSITION_24 | EXTICR[2] */
-#define LL_EXTI_CONFIG_LINE12              ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
-#define LL_EXTI_CONFIG_LINE13              ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT)  | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
-#define LL_EXTI_CONFIG_LINE14              ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)  /*!< EXTI_POSITION_16 | EXTICR[3] */
-#define LL_EXTI_CONFIG_LINE15              ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)  /*!< EXTI_POSITION_24 | EXTICR[3] */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
-#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
-#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
-  * @{
-  */
-#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
-
-/**
-  * @}
-  */
-
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in EXTI register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in EXTI register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->IMR1, ExtiLine);
-}
-
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63
-  * @note The reset value for the direct lines (lines 32 & 33)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->IMR2, ExtiLine);
-}
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->IMR1, ExtiLine);
-}
-
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63
-  * @note The reset value for the direct lines (lines 32 & 33)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->IMR2, ExtiLine);
-}
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
-  * @note The reset value for the direct lines (lines 32 & 33)
-  *       is set to 1 in order to enable the interrupt by default.
-  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->EMR1, ExtiLine);
-
-}
-
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63
-  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->EMR2, ExtiLine);
-}
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->EMR1, ExtiLine);
-}
-
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63
-  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->EMR2, ExtiLine);
-}
-#endif
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
-  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_23
-  *         @arg @ref LL_EXTI_LINE_25
-  *         @arg @ref LL_EXTI_LINE_26
-  *         @arg @ref LL_EXTI_LINE_27
-  *         @arg @ref LL_EXTI_LINE_28
-  *         @arg @ref LL_EXTI_LINE_29
-  *         @arg @ref LL_EXTI_LINE_30
-  *         @arg @ref LL_EXTI_LINE_31
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
-  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_32
-  *         @arg @ref LL_EXTI_LINE_33
-  *         @arg @ref LL_EXTI_LINE_34
-  *         @arg @ref LL_EXTI_LINE_35
-  *         @arg @ref LL_EXTI_LINE_36
-  *         @arg @ref LL_EXTI_LINE_ALL_32_63
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->RTSR1, ExtiLine);
-
-}
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->RTSR2, ExtiLine);
-
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->RTSR1, ExtiLine);
-
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->RTSR2, ExtiLine);
-
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63
-  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->FTSR1, ExtiLine);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->FTSR2, ExtiLine);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for the same interrupt line.
-  *       In this case, both generate a trigger condition.
-  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->FTSR1, ExtiLine);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for the same interrupt line.
-  *       In this case, both generate a trigger condition.
-  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->FTSR2, ExtiLine);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63
-  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
-  * @{
-  */
-
-/**
-  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
-  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
-  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
-  *       resulting in an interrupt request generation.
-  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
-  *       register (by writing a 1 into the bit)
-  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->SWIER1, ExtiLine);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63
-  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
-  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
-  *       resulting in an interrupt request generation.
-  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
-  *       register (by writing a 1 into the bit)
-  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->SWIER2, ExtiLine);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31
-  * @note This bit is set when the falling edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll FPR1          FPIFx           LL_EXTI_IsActiveFallingFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Check if the ExtLine Falling Flag is set or not for Lines in range 32 to 63
-  * @note This bit is set when the falling edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll FPR2          FPIFx           LL_EXTI_IsActiveFallingFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->FPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @brief  Read ExtLine Combination Falling Flag for Lines in range 0 to 31
-  * @note This bit is set when the falling edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll FPR1          FPIFx           LL_EXTI_ReadFallingFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->FPR1, ExtiLine));
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Read ExtLine Combination Falling Flag for Lines in range 32 to 63
-  * @note This bit is set when the falling edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll FPR2          FPIFx           LL_EXTI_ReadFallingFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->FPR2, ExtiLine));
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @brief  Clear ExtLine Falling Flags  for Lines in range 0 to 31
-  * @note This bit is set when the falling edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll FPR1          FPIFx           LL_EXTI_ClearFallingFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->FPR1, ExtiLine);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Clear ExtLine Falling Flags  for Lines in range 32 to 63
-  * @note This bit is set when the falling edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll FPR2          FPIFx           LL_EXTI_ClearFallingFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->FPR2, ExtiLine);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @brief  Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31
-  * @note This bit is set when the Rising edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll RPR1          RPIFx           LL_EXTI_IsActiveRisingFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63
-  * @note This bit is set when the Rising edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll RPR2          RPIFx           LL_EXTI_IsActiveRisingFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t ExtiLine)
-{
-  return ((READ_BIT(EXTI->RPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @brief  Read ExtLine Combination Rising Flag for Lines in range 0 to 31
-  * @note This bit is set when the Rising edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll RPR1          RPIFx           LL_EXTI_ReadRisingFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->RPR1, ExtiLine));
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Read ExtLine Combination Rising Flag for Lines in range 32 to 63
-  * @note This bit is set when the Rising edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll RPR2          RPIFx           LL_EXTI_ReadRisingFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->RPR2, ExtiLine));
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @brief  Clear ExtLine Rising Flags  for Lines in range 0 to 31
-  * @note This bit is set when the Rising edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll RPR1          RPIFx           LL_EXTI_ClearRisingFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_20
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->RPR1, ExtiLine);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Clear ExtLine Rising Flags  for Lines in range 32 to 63
-  * @note This bit is set when the Rising edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll RPR2          RPIFx           LL_EXTI_ClearRisingFlag_32_63
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_34
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->RPR2, ExtiLine);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-/**
-  * @}
-  */
-/** @defgroup EXTI_LL_EF_Config EF configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Configure source input for the EXTI external interrupt.
-  * @rmtoll EXTI_EXTICR1 EXTI0         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR1 EXTI1         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR1 EXTI2         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR1 EXTI3         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR2 EXTI4         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR2 EXTI5         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR2 EXTI6         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR2 EXTI7         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR3 EXTI8         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR3 EXTI9         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR3 EXTI10        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR3 EXTI11        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR4 EXTI12        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR4 EXTI13        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR4 EXTI14        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR4 EXTI15        LL_EXTI_SetEXTISource
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref EXTI_LL_EC_CONFIG_PORT
-  *
-  *         (*) value not defined in all devices
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_CONFIG_LINE0
-  *         @arg @ref LL_EXTI_CONFIG_LINE1
-  *         @arg @ref LL_EXTI_CONFIG_LINE2
-  *         @arg @ref LL_EXTI_CONFIG_LINE3
-  *         @arg @ref LL_EXTI_CONFIG_LINE4
-  *         @arg @ref LL_EXTI_CONFIG_LINE5
-  *         @arg @ref LL_EXTI_CONFIG_LINE6
-  *         @arg @ref LL_EXTI_CONFIG_LINE7
-  *         @arg @ref LL_EXTI_CONFIG_LINE8
-  *         @arg @ref LL_EXTI_CONFIG_LINE9
-  *         @arg @ref LL_EXTI_CONFIG_LINE10
-  *         @arg @ref LL_EXTI_CONFIG_LINE11
-  *         @arg @ref LL_EXTI_CONFIG_LINE12
-  *         @arg @ref LL_EXTI_CONFIG_LINE13
-  *         @arg @ref LL_EXTI_CONFIG_LINE14
-  *         @arg @ref LL_EXTI_CONFIG_LINE15
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line)
-{
-  MODIFY_REG(EXTI->EXTICR[Line & 0x03u], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
-}
-
-/**
-  * @brief  Get the configured defined for specific EXTI Line
-  * @rmtoll EXTI_EXTICR1 EXTI0         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR1 EXTI1         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR1 EXTI2         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR1 EXTI3         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR2 EXTI4         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR2 EXTI5         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR2 EXTI6         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR2 EXTI7         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR3 EXTI8         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR3 EXTI9         LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR3 EXTI10        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR3 EXTI11        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR4 EXTI12        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR4 EXTI13        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR4 EXTI14        LL_EXTI_SetEXTISource\n
-  *         EXTI_EXTICR4 EXTI15        LL_EXTI_SetEXTISource
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_CONFIG_LINE0
-  *         @arg @ref LL_EXTI_CONFIG_LINE1
-  *         @arg @ref LL_EXTI_CONFIG_LINE2
-  *         @arg @ref LL_EXTI_CONFIG_LINE3
-  *         @arg @ref LL_EXTI_CONFIG_LINE4
-  *         @arg @ref LL_EXTI_CONFIG_LINE5
-  *         @arg @ref LL_EXTI_CONFIG_LINE6
-  *         @arg @ref LL_EXTI_CONFIG_LINE7
-  *         @arg @ref LL_EXTI_CONFIG_LINE8
-  *         @arg @ref LL_EXTI_CONFIG_LINE9
-  *         @arg @ref LL_EXTI_CONFIG_LINE10
-  *         @arg @ref LL_EXTI_CONFIG_LINE11
-  *         @arg @ref LL_EXTI_CONFIG_LINE12
-  *         @arg @ref LL_EXTI_CONFIG_LINE13
-  *         @arg @ref LL_EXTI_CONFIG_LINE14
-  *         @arg @ref LL_EXTI_CONFIG_LINE15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref EXTI_LL_EC_CONFIG_PORT
-  *
-  *         (*) value not defined in all devices
-  */
-__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line)
-{
-  return (READ_BIT(EXTI->EXTICR[Line & 0x03u], (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
-}
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-uint32_t LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* EXTI */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_gpio.h

@@ -1,960 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_gpio.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_GPIO_H
-#define STM32G0xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
-
-/** @defgroup GPIO_LL GPIO
-  * @{
-  */
-/** MISRA C:2012 deviation rule has been granted for following rules:
-  * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
-  * which may be out of array bounds [..,UNKNOWN] in following APIs:
-  * LL_GPIO_GetAFPin_0_7
-  * LL_GPIO_SetAFPin_0_7
-  * LL_GPIO_SetAFPin_8_15
-  * LL_GPIO_GetAFPin_8_15
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL GPIO Init Structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
-                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
-  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
-
-  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
-
-  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
-
-  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
-
-  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_AF.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
-} LL_GPIO_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
-  * @{
-  */
-#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */
-#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */
-#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */
-#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */
-#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */
-#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */
-#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */
-#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */
-#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */
-#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */
-#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */
-#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */
-#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */
-#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */
-#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */
-#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \
-                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \
-                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \
-                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
-                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
-                                           GPIO_BSRR_BS15) /*!< Select all pins */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */
-#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */
-#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
-  * @{
-  */
-#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
-  * @{
-  */
-#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
-#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */
-#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */
-/**
-  * @}
-  */
-#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW
-#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM
-#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH
-#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH
-
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
-  * @{
-  */
-#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
-#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
-#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_AF Alternate Function
-  * @{
-  */
-#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
-#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx)
-#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
-#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
-#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
-#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
-  * @{
-  */
-
-/**
-  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
-  MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
-}
-
-/**
-  * @brief  Return gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
-}
-
-/**
-  * @brief  Configure gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @param  OutputType This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
-{
-  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
-}
-
-/**
-  * @brief  Return gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
-}
-
-/**
-  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Speed This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
-{
-  MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));
-}
-
-/**
-  * @brief  Return gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));
-}
-
-/**
-  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Pull This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
-{
-  MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
-}
-
-/**
-  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @note   Possible values are from AF0 to AF7 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
-             ((((Pin * Pin) * Pin) * Pin) * Alternate));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
-                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF7 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
-             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF7 depending on target.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
-                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
-                                 (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
-}
-
-
-/**
-  * @brief  Lock configuration of several pins for a dedicated port.
-  * @note   When the lock sequence has been applied on a port bit, the
-  *         value of this port bit can no longer be modified until the
-  *         next reset.
-  * @note   Each lock bit freezes a specific configuration register
-  *         (control and alternate function registers).
-  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  __IO uint32_t temp;
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  WRITE_REG(GPIOx->LCKR, PinMask);
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  /* Read LCKK register. This read is mandatory to complete key lock sequence */
-  temp = READ_REG(GPIOx->LCKR);
-  (void) temp;
-}
-
-/**
-  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
-  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
-  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
-  * @param  GPIOx GPIO Port
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
-{
-  return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
-  * @{
-  */
-
-/**
-  * @brief  Return full input data register value for a dedicated port.
-  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
-  * @param  GPIOx GPIO Port
-  * @retval Input data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->IDR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Write output data register for the port.
-  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
-  * @param  GPIOx GPIO Port
-  * @param  PortValue Level value for each pin of the port
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
-{
-  WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
-  * @brief  Return full output data register value for a dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
-  * @param  GPIOx GPIO Port
-  * @retval Output data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set several pins to high level on dedicated gpio port.
-  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  WRITE_REG(GPIOx->BSRR, PinMask);
-}
-
-/**
-  * @brief  Set several pins to low level on dedicated gpio port.
-  * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  WRITE_REG(GPIOx->BRR, PinMask);
-}
-
-/**
-  * @brief  Toggle data value for several pin of dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  uint32_t odr = READ_REG(GPIOx->ODR);
-  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
-}
-
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_i2c.h

@@ -1,2275 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_i2c.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2C LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_I2C_H
-#define STM32G0xx_LL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (I2C1) || defined (I2C2) || defined (I2C3)
-
-/** @defgroup I2C_LL I2C
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_LL_Private_Constants I2C Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_Private_Macros I2C Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
-  * @{
-  */
-typedef struct
-{
-  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
-                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetMode(). */
-
-  uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
-                                     This parameter must be set by referring to the STM32CubeMX Tool and
-                                     the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetTiming(). */
-
-  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
-                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
-
-                                     This feature can be modified afterwards using unitary functions
-                                     @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
-
-  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
-                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetDigitalFilter(). */
-
-  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
-                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetOwnAddress1(). */
-
-  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
-                                     match code or next received byte.
-                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_AcknowledgeNextData(). */
-
-  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
-                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
-
-                                     This feature can be modified afterwards using unitary function
-                                     @ref LL_I2C_SetOwnAddress1(). */
-} LL_I2C_InitTypeDef;
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_I2C_WriteReg function
-  * @{
-  */
-#define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
-#define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
-#define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
-#define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
-#define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
-#define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
-#define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
-#define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
-#define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_I2C_ReadReg function
-  * @{
-  */
-#define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
-#define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
-#define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
-#define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
-#define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
-#define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
-#define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
-#define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
-#define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
-#define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
-#define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
-#define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
-#define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
-#define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
-#define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
-  * @{
-  */
-#define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
-#define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
-#define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
-#define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
-#define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
-#define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
-#define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
-  * @{
-  */
-#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
-#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
-#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
-                                                                         (Default address not acknowledge)        */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
-  * @{
-  */
-#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
-#define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
-  * @{
-  */
-#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
-#define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
-  * @{
-  */
-#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
-#define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
-  * @{
-  */
-#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
-#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
-#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
-#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
-                                                                         All Address2 are acknowledged.        */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
-  * @{
-  */
-#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
-#define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
-  * @{
-  */
-#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
-#define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
-  * @{
-  */
-#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
-#define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_MODE Transfer End Mode
-  * @{
-  */
-#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
-#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
-                                                                          with no HW PEC comparison.  */
-#define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
-                                                                          with no HW PEC comparison.  */
-#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
-                                                                          with HW PEC comparison.     */
-#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
-                                                                          with HW PEC comparison.     */
-#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
-                                                                          with HW PEC comparison.     */
-#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
-/*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
-#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
-/*!< Enable SMBUS Software end mode with HW PEC comparison.    */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
-  * @{
-  */
-#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
-/*!< Don't Generate Stop and Start condition. */
-#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
-/*!< Generate Stop condition (Size should be set to 0).      */
-#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-/*!< Generate Start for read request. */
-#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
-/*!< Generate Start for write request. */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-/*!< Generate Restart for read request, slave 7Bit address.  */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
-/*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
-                                                       I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
-/*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
-/*!< Generate Restart for write request, slave 10Bit address.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
-  * @{
-  */
-#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
-                                                                          slave enters receiver mode.  */
-#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
-                                                                          slave enters transmitter mode.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
-  * @{
-  */
-#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
-                                                                          transmission */
-#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
-                                                                          reception */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
-  * @{
-  */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
-                                                                          SCL low level timeout.              */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
-                                                                          both SCL and SDA high level timeout.*/
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
-  * @{
-  */
-#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
-#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
-                                                                                       enable bit                   */
-#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
-                                                       I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
-(extended clock) enable bits */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in I2C register
-  * @param  __INSTANCE__ I2C Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in I2C register
-  * @param  __INSTANCE__ I2C Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
-  * @{
-  */
-/**
-  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
-  * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
-  * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
-                           (tscldel = (SCLDEL+1)xtpresc)
-  * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
-                           (tsdadel = SDADELxtpresc)
-  * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
-                            (tsclh = (SCLH+1)xtpresc)
-  * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
-                            (tscll = (SCLL+1)xtpresc)
-  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
-  */
-#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
-  ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
-   (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
-   (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
-   (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
-   (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable I2C peripheral (PE = 1).
-  * @rmtoll CR1          PE            LL_I2C_Enable
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
-  * @brief  Disable I2C peripheral (PE = 0).
-  * @note   When PE = 0, the I2C SCL and SDA lines are released.
-  *         Internal state machines and status bits are put back to their reset value.
-  *         When cleared, PE must be kept low for at least 3 APB clock cycles.
-  * @rmtoll CR1          PE            LL_I2C_Disable
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
-  * @brief  Check if the I2C peripheral is enabled or disabled.
-  * @rmtoll CR1          PE            LL_I2C_IsEnabled
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure Noise Filters (Analog and Digital).
-  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
-  *         The filters can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
-  *         CR1          DNF           LL_I2C_ConfigFilters
-  * @param  I2Cx I2C Instance.
-  * @param  AnalogFilter This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
-  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
-  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
-                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
-  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
-  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
-}
-
-/**
-  * @brief  Configure Digital Noise Filter.
-  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
-  *         This filter can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
-  * @param  I2Cx I2C Instance.
-  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
-                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
-  *         This parameter is used to configure the digital noise filter on SDA and SCL input.
-  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
-}
-
-/**
-  * @brief  Get the current Digital Noise Filter configuration.
-  * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
-}
-
-/**
-  * @brief  Enable Analog Noise Filter.
-  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
-}
-
-/**
-  * @brief  Disable Analog Noise Filter.
-  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
-}
-
-/**
-  * @brief  Check if Analog Noise Filter is enabled or disabled.
-  * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA transmission requests.
-  * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA transmission requests.
-  * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA transmission requests are enabled or disabled.
-  * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA reception requests.
-  * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA reception requests.
-  * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA reception requests are enabled or disabled.
-  * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
-  *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
-  * @param  I2Cx I2C Instance
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
-  *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
-{
-  uint32_t data_reg_addr;
-
-  if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
-  {
-    /* return address of TXDR register */
-    data_reg_addr = (uint32_t) &(I2Cx->TXDR);
-  }
-  else
-  {
-    /* return address of RXDR register */
-    data_reg_addr = (uint32_t) &(I2Cx->RXDR);
-  }
-
-  return data_reg_addr;
-}
-
-/**
-  * @brief  Enable Clock stretching.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
-  * @brief  Disable Clock stretching.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
-  * @brief  Check if Clock stretching is enabled or disabled.
-  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable hardware byte control in slave mode.
-  * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
-}
-
-/**
-  * @brief  Disable hardware byte control in slave mode.
-  * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
-}
-
-/**
-  * @brief  Check if hardware byte control in slave mode is enabled or disabled.
-  * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Wakeup from STOP.
-  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
-  *         WakeUpFromStop feature is supported by the I2Cx Instance.
-  * @note   This bit can only be programmed when Digital Filter is disabled.
-  * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
-}
-
-/**
-  * @brief  Disable Wakeup from STOP.
-  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
-  *         WakeUpFromStop feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
-}
-
-/**
-  * @brief  Check if Wakeup from STOP is enabled or disabled.
-  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
-  *         WakeUpFromStop feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable General Call.
-  * @note   When enabled the Address 0x00 is ACKed.
-  * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
-}
-
-/**
-  * @brief  Disable General Call.
-  * @note   When disabled the Address 0x00 is NACKed.
-  * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
-}
-
-/**
-  * @brief  Check if General Call is enabled or disabled.
-  * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
-  * @note   Changing this bit is not allowed, when the START bit is set.
-  * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
-  * @param  I2Cx I2C Instance.
-  * @param  AddressingMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
-}
-
-/**
-  * @brief  Get the Master addressing mode.
-  * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
-  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
-}
-
-/**
-  * @brief  Set the Own Address1.
-  * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
-  *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
-  * @param  OwnAddrSize This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
-  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
-{
-  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
-}
-
-/**
-  * @brief  Enable acknowledge on Own Address1 match address.
-  * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
-}
-
-/**
-  * @brief  Disable acknowledge on Own Address1 match address.
-  * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
-}
-
-/**
-  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
-  * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the 7bits Own Address2.
-  * @note   This action has no effect if own address2 is enabled.
-  * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
-  *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
-  * @param  OwnAddrMask This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
-  *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
-{
-  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
-}
-
-/**
-  * @brief  Enable acknowledge on Own Address2 match address.
-  * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
-}
-
-/**
-  * @brief  Disable  acknowledge on Own Address2 match address.
-  * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
-}
-
-/**
-  * @brief  Check if Own Address1 acknowledge is enabled or disabled.
-  * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the SDA setup, hold time and the SCL high, low period.
-  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
-  * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
-  * @param  I2Cx I2C Instance.
-  * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
-  * @note   This parameter is computed with the STM32CubeMX Tool.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
-{
-  WRITE_REG(I2Cx->TIMINGR, Timing);
-}
-
-/**
-  * @brief  Get the Timing Prescaler setting.
-  * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
-}
-
-/**
-  * @brief  Get the SCL low period setting.
-  * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
-}
-
-/**
-  * @brief  Get the SCL high period setting.
-  * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
-}
-
-/**
-  * @brief  Get the SDA hold time.
-  * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
-}
-
-/**
-  * @brief  Get the SDA setup time.
-  * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
-}
-
-/**
-  * @brief  Configure peripheral mode.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
-  *         CR1          SMBDEN        LL_I2C_SetMode
-  * @param  I2Cx I2C Instance.
-  * @param  PeripheralMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_I2C
-  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
-{
-  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
-}
-
-/**
-  * @brief  Get peripheral mode.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
-  *         CR1          SMBDEN        LL_I2C_GetMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_I2C
-  *         @arg @ref LL_I2C_MODE_SMBUS_HOST
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
-  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
-}
-
-/**
-  * @brief  Enable SMBus alert (Host or Device mode)
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   SMBus Device mode:
-  *         - SMBus Alert pin is drived low and
-  *           Alert Response Address Header acknowledge is enabled.
-  *         SMBus Host mode:
-  *         - SMBus Alert pin management is supported.
-  * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
-}
-
-/**
-  * @brief  Disable SMBus alert (Host or Device mode)
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   SMBus Device mode:
-  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
-  *           Alert Response Address Header acknowledge is disabled.
-  *         SMBus Host mode:
-  *         - SMBus Alert pin management is not supported.
-  * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
-}
-
-/**
-  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable SMBus Packet Error Calculation (PEC).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
-}
-
-/**
-  * @brief  Disable SMBus Packet Error Calculation (PEC).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
-}
-
-/**
-  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the SMBus Clock Timeout.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
-  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
-  *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
-  *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
-  * @param  TimeoutAMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
-  * @param  TimeoutB
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
-                                               uint32_t TimeoutB)
-{
-  MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
-             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
-}
-
-/**
-  * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   These bits can only be programmed when TimeoutA is disabled.
-  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
-{
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
-}
-
-/**
-  * @brief  Get the SMBus Clock TimeoutA setting.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
-}
-
-/**
-  * @brief  Set the SMBus Clock TimeoutA mode.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This bit can only be programmed when TimeoutA is disabled.
-  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutAMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
-{
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
-}
-
-/**
-  * @brief  Get the SMBus Clock TimeoutA mode.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
-}
-
-/**
-  * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   These bits can only be programmed when TimeoutB is disabled.
-  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
-  * @param  I2Cx I2C Instance.
-  * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
-{
-  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
-}
-
-/**
-  * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
-}
-
-/**
-  * @brief  Enable the SMBus Clock Timeout.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
-  *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  ClockTimeout This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
-  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
-  SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
-}
-
-/**
-  * @brief  Disable the SMBus Clock Timeout.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
-  *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  ClockTimeout This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
-  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
-  CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
-}
-
-/**
-  * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
-  *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
-  * @param  I2Cx I2C Instance.
-  * @param  ClockTimeout This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
-  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
-  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
-{
-  return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
-                    (ClockTimeout)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable TXIS interrupt.
-  * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
-}
-
-/**
-  * @brief  Disable TXIS interrupt.
-  * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
-}
-
-/**
-  * @brief  Check if the TXIS Interrupt is enabled or disabled.
-  * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable RXNE interrupt.
-  * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
-}
-
-/**
-  * @brief  Disable RXNE interrupt.
-  * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
-}
-
-/**
-  * @brief  Check if the RXNE Interrupt is enabled or disabled.
-  * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Address match interrupt (slave mode only).
-  * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
-}
-
-/**
-  * @brief  Disable Address match interrupt (slave mode only).
-  * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
-}
-
-/**
-  * @brief  Check if Address match interrupt is enabled or disabled.
-  * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Not acknowledge received interrupt.
-  * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
-}
-
-/**
-  * @brief  Disable Not acknowledge received interrupt.
-  * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
-}
-
-/**
-  * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
-  * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable STOP detection interrupt.
-  * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
-}
-
-/**
-  * @brief  Disable STOP detection interrupt.
-  * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
-}
-
-/**
-  * @brief  Check if STOP detection interrupt is enabled or disabled.
-  * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Transfer Complete interrupt.
-  * @note   Any of these events will generate interrupt :
-  *         Transfer Complete (TC)
-  *         Transfer Complete Reload (TCR)
-  * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
-}
-
-/**
-  * @brief  Disable Transfer Complete interrupt.
-  * @note   Any of these events will generate interrupt :
-  *         Transfer Complete (TC)
-  *         Transfer Complete Reload (TCR)
-  * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
-}
-
-/**
-  * @brief  Check if Transfer Complete interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Error interrupts.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   Any of these errors will generate interrupt :
-  *         Arbitration Loss (ARLO)
-  *         Bus Error detection (BERR)
-  *         Overrun/Underrun (OVR)
-  *         SMBus Timeout detection (TIMEOUT)
-  *         SMBus PEC error detection (PECERR)
-  *         SMBus Alert pin event detection (ALERT)
-  * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
-}
-
-/**
-  * @brief  Disable Error interrupts.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   Any of these errors will generate interrupt :
-  *         Arbitration Loss (ARLO)
-  *         Bus Error detection (BERR)
-  *         Overrun/Underrun (OVR)
-  *         SMBus Timeout detection (TIMEOUT)
-  *         SMBus PEC error detection (PECERR)
-  *         SMBus Alert pin event detection (ALERT)
-  * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
-}
-
-/**
-  * @brief  Check if Error interrupts are enabled or disabled.
-  * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
-  * @{
-  */
-
-/**
-  * @brief  Indicate the status of Transmit data register empty flag.
-  * @note   RESET: When next data is written in Transmit data register.
-  *         SET: When Transmit data register is empty.
-  * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Transmit interrupt flag.
-  * @note   RESET: When next data is written in Transmit data register.
-  *         SET: When Transmit data register is empty.
-  * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Receive data register not empty flag.
-  * @note   RESET: When Receive data register is read.
-  *         SET: When the received data is copied in Receive data register.
-  * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Address matched flag (slave mode).
-  * @note   RESET: Clear default value.
-  *         SET: When the received slave address matched with one of the enabled slave address.
-  * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Not Acknowledge received flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a NACK is received after a byte transmission.
-  * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Stop detection flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a Stop condition is detected.
-  * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Transfer complete flag (master mode).
-  * @note   RESET: Clear default value.
-  *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
-  * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Transfer complete flag (master mode).
-  * @note   RESET: Clear default value.
-  *         SET: When RELOAD=1 and NBYTES date have been transferred.
-  * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Bus error flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a misplaced Start or Stop condition is detected.
-  * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Arbitration lost flag.
-  * @note   RESET: Clear default value.
-  *         SET: When arbitration lost.
-  * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
-  * @note   RESET: Clear default value.
-  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
-  * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of SMBus PEC error flag in reception.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: Clear default value.
-  *         SET: When the received PEC does not match with the PEC register content.
-  * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of SMBus Timeout detection flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: Clear default value.
-  *         SET: When a timeout or extended clock timeout occurs.
-  * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of SMBus alert flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   RESET: Clear default value.
-  *         SET: When SMBus host configuration, SMBus alert enabled and
-  *              a falling edge event occurs on SMBA pin.
-  * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate the status of Bus Busy flag.
-  * @note   RESET: Clear default value.
-  *         SET: When a Start condition is detected.
-  * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Address Matched flag.
-  * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
-}
-
-/**
-  * @brief  Clear Not Acknowledge flag.
-  * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
-}
-
-/**
-  * @brief  Clear Stop detection flag.
-  * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
-}
-
-/**
-  * @brief  Clear Transmit data register empty flag (TXE).
-  * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
-  * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
-{
-  WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
-}
-
-/**
-  * @brief  Clear Bus error flag.
-  * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
-}
-
-/**
-  * @brief  Clear Arbitration lost flag.
-  * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
-}
-
-/**
-  * @brief  Clear Overrun/Underrun flag.
-  * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
-}
-
-/**
-  * @brief  Clear SMBus PEC error flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
-}
-
-/**
-  * @brief  Clear SMBus Timeout detection flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
-}
-
-/**
-  * @brief  Clear SMBus Alert flag.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable automatic STOP condition generation (master mode).
-  * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
-  *         This bit has no effect in slave mode or when RELOAD bit is set.
-  * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
-}
-
-/**
-  * @brief  Disable automatic STOP condition generation (master mode).
-  * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
-  * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
-}
-
-/**
-  * @brief  Check if automatic STOP condition is enabled or disabled.
-  * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable reload mode (master mode).
-  * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
-  * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
-}
-
-/**
-  * @brief  Disable reload mode (master mode).
-  * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
-  * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
-}
-
-/**
-  * @brief  Check if reload mode is enabled or disabled.
-  * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the number of bytes for transfer.
-  * @note   Changing these bits when START bit is set is not allowed.
-  * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
-  * @param  I2Cx I2C Instance.
-  * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
-}
-
-/**
-  * @brief  Get the number of bytes configured for transfer.
-  * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
-}
-
-/**
-  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
-            or next received byte.
-  * @note   Usage in Slave mode only.
-  * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
-  * @param  I2Cx I2C Instance.
-  * @param  TypeAcknowledge This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ACK
-  *         @arg @ref LL_I2C_NACK
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
-}
-
-/**
-  * @brief  Generate a START or RESTART condition
-  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
-  *         This action has no effect when RELOAD is set.
-  * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_START);
-}
-
-/**
-  * @brief  Generate a STOP condition after the current byte transfer (master mode).
-  * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
-}
-
-/**
-  * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
-  * @note   The master sends the complete 10bit slave address read sequence :
-  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
-            in Read direction.
-  * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
-{
-  CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
-}
-
-/**
-  * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
-  * @note   The master only sends the first 7 bits of 10bit address in Read direction.
-  * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
-}
-
-/**
-  * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
-  * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the transfer direction (master mode).
-  * @note   Changing these bits when START bit is set is not allowed.
-  * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
-  * @param  I2Cx I2C Instance.
-  * @param  TransferRequest This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_REQUEST_WRITE
-  *         @arg @ref LL_I2C_REQUEST_READ
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
-}
-
-/**
-  * @brief  Get the transfer direction requested (master mode).
-  * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_REQUEST_WRITE
-  *         @arg @ref LL_I2C_REQUEST_READ
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
-}
-
-/**
-  * @brief  Configure the slave address for transfer (master mode).
-  * @note   Changing these bits when START bit is set is not allowed.
-  * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
-  * @param  I2Cx I2C Instance.
-  * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
-}
-
-/**
-  * @brief  Get the slave address programmed for transfer.
-  * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x0 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
-}
-
-/**
-  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
-  * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
-  *         CR2          ADD10         LL_I2C_HandleTransfer\n
-  *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
-  *         CR2          START         LL_I2C_HandleTransfer\n
-  *         CR2          STOP          LL_I2C_HandleTransfer\n
-  *         CR2          RELOAD        LL_I2C_HandleTransfer\n
-  *         CR2          NBYTES        LL_I2C_HandleTransfer\n
-  *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
-  *         CR2          HEAD10R       LL_I2C_HandleTransfer
-  * @param  I2Cx I2C Instance.
-  * @param  SlaveAddr Specifies the slave address to be programmed.
-  * @param  SlaveAddrSize This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
-  *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
-  * @param  TransferSize Specifies the number of bytes to be programmed.
-  *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
-  * @param  EndMode This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_MODE_RELOAD
-  *         @arg @ref LL_I2C_MODE_AUTOEND
-  *         @arg @ref LL_I2C_MODE_SOFTEND
-  *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
-  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
-  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
-  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
-  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
-  * @param  Request This parameter can be one of the following values:
-  *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
-  *         @arg @ref LL_I2C_GENERATE_STOP
-  *         @arg @ref LL_I2C_GENERATE_START_READ
-  *         @arg @ref LL_I2C_GENERATE_START_WRITE
-  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
-  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
-  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
-  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
-                                           uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
-{
-  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
-             (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
-             I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
-             I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
-             SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
-}
-
-/**
-  * @brief  Indicate the value of transfer direction (slave mode).
-  * @note   RESET: Write transfer, Slave enters in receiver mode.
-  *         SET: Read transfer, Slave enters in transmitter mode.
-  * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
-  * @param  I2Cx I2C Instance.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2C_DIRECTION_WRITE
-  *         @arg @ref LL_I2C_DIRECTION_READ
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
-}
-
-/**
-  * @brief  Return the slave matched address.
-  * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
-}
-
-/**
-  * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
-            or an Address Matched is received.
-  *         This bit has no effect when RELOAD bit is set.
-  *         This bit has no effect in device mode when SBC bit is not set.
-  * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
-  * @param  I2Cx I2C Instance.
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
-  SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
-}
-
-/**
-  * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
-  * @param  I2Cx I2C Instance.
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
-  return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the SMBus Packet Error byte calculated.
-  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
-  *         SMBus feature is supported by the I2Cx Instance.
-  * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
-{
-  return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
-}
-
-/**
-  * @brief  Read Receive Data register.
-  * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
-  * @param  I2Cx I2C Instance.
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
-{
-  return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
-}
-
-/**
-  * @brief  Write in Transmit Data Register .
-  * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
-  * @param  I2Cx I2C Instance.
-  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
-{
-  WRITE_REG(I2Cx->TXDR, Data);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* I2C1 || I2C2 || I2C3 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_pwr.h

@@ -1,1529 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_pwr.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_PWR_H
-#define STM32G0xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
-  * @{
-  */
-#define LL_PWR_SCR_CSBF                    PWR_SCR_CSBF
-#define LL_PWR_SCR_CWUF                    PWR_SCR_CWUF
-#define LL_PWR_SCR_CWUF6                   PWR_SCR_CWUF6
-#define LL_PWR_SCR_CWUF5                   PWR_SCR_CWUF5
-#define LL_PWR_SCR_CWUF4                   PWR_SCR_CWUF4
-#if defined(PWR_CR3_EWUP3)
-#define LL_PWR_SCR_CWUF3                   PWR_SCR_CWUF3
-#endif /* PWR_CR3_EWUP3 */
-#define LL_PWR_SCR_CWUF2                   PWR_SCR_CWUF2
-#define LL_PWR_SCR_CWUF1                   PWR_SCR_CWUF1
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
-  * @{
-  */
-#define LL_PWR_SR1_WUFI                    PWR_SR1_WUFI
-#define LL_PWR_SR1_SBF                     PWR_SR1_SBF
-#define LL_PWR_SR1_WUF6                    PWR_SR1_WUF6
-#define LL_PWR_SR1_WUF5                    PWR_SR1_WUF5
-#define LL_PWR_SR1_WUF4                    PWR_SR1_WUF4
-#if defined(PWR_CR3_EWUP3)
-#define LL_PWR_SR1_WUF3                    PWR_SR1_WUF3
-#endif /* PWR_CR3_EWUP3 */
-#define LL_PWR_SR1_WUF2                    PWR_SR1_WUF2
-#define LL_PWR_SR1_WUF1                    PWR_SR1_WUF1
-#if defined(PWR_SR2_PVDO)
-#define LL_PWR_SR2_PVDO                    PWR_SR2_PVDO
-#endif /* PWR_SR2_PVDO */
-#define LL_PWR_SR2_VOSF                    PWR_SR2_VOSF
-#define LL_PWR_SR2_REGLPF                  PWR_SR2_REGLPF
-#define LL_PWR_SR2_REGLPS                  PWR_SR2_REGLPS
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
-  * @{
-  */
-#define LL_PWR_REGU_VOLTAGE_SCALE1         PWR_CR1_VOS_0
-#define LL_PWR_REGU_VOLTAGE_SCALE2         PWR_CR1_VOS_1
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
-  * @{
-  */
-#define LL_PWR_MODE_STOP0                  (0x00000000UL)
-#define LL_PWR_MODE_STOP1                  (PWR_CR1_LPMS_0)
-#define LL_PWR_MODE_STANDBY                (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0)
-#if defined (PWR_CR1_LPMS_2)
-#define LL_PWR_MODE_SHUTDOWN               (PWR_CR1_LPMS_2)
-#endif /* PWR_CR1_LPMS_2 */
-/**
-  * @}
-  */
-
-#if defined(PWR_CR2_PVDE)
-/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
-  * @{
-  */
-#define LL_PWR_PVDLLEVEL_0                  0x000000000u                                /* VPVD0 > 2.05 V */
-#define LL_PWR_PVDLLEVEL_1                  (PWR_CR2_PVDFT_0)                           /* VPVD0 > 2.2 V */
-#define LL_PWR_PVDLLEVEL_2                  (PWR_CR2_PVDFT_1)                           /* VPVD1 > 2.36 V */
-#define LL_PWR_PVDLLEVEL_3                  (PWR_CR2_PVDFT_1 | PWR_CR2_PVDFT_0)         /* VPVD2 > 2.52 V */
-#define LL_PWR_PVDLLEVEL_4                  (PWR_CR2_PVDFT_2)                           /* VPVD3 > 2.64 V */
-#define LL_PWR_PVDLLEVEL_5                  (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0)         /* VPVD4 > 2.81 V */
-#define LL_PWR_PVDLLEVEL_6                  (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1)         /* VPVD5 > 2.91 V */
-
-#define LL_PWR_PVDHLEVEL_0                  0x00000000u                                 /* VPDD0 > 2.15 V */
-#define LL_PWR_PVDHLEVEL_1                  (PWR_CR2_PVDRT_0)                           /* VPVD1 > 2.3 V */
-#define LL_PWR_PVDHLEVEL_2                  (PWR_CR2_PVDRT_1)                           /* VPVD1 > 2.46 V */
-#define LL_PWR_PVDHLEVEL_3                  (PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)         /* VPVD2 > 2.62 V */
-#define LL_PWR_PVDHLEVEL_4                  (PWR_CR2_PVDRT_2)                           /* VPVD3 > 2.74 V */
-#define LL_PWR_PVDHLEVEL_5                  (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0)         /* VPVD4 > 2.91 V */
-#define LL_PWR_PVDHLEVEL_6                  (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1)         /* VPVD5 > 3.01 V */
-#define LL_PWR_PVDHLEVEL_7                  (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)  /* External input analog voltage   (Compare internally to VREFINT) */
-/**
-  * @}
-  */
-#endif /* PWR_CR2_PVDE */
-
-#if defined(PWR_PVM_SUPPORT)
-/** @defgroup PWR_LL_EC_PVM_IP PVM_IP
-  * @{
-  */
-#define LL_PWR_PVM_USB                  PWR_CR2_PVMEN_USB                           /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */
-/**
-  * @}
-  */
-#endif /* PWR_PVM_SUPPORT */
-
-/** @defgroup PWR_LL_EC_WAKEUP WAKEUP
-  * @{
-  */
-#define LL_PWR_WAKEUP_PIN1                 (PWR_CR3_EWUP1)
-#define LL_PWR_WAKEUP_PIN2                 (PWR_CR3_EWUP2)
-#if defined(PWR_CR3_EWUP3)
-#define LL_PWR_WAKEUP_PIN3                 (PWR_CR3_EWUP3)
-#endif /* PWR_CR3_EWUP3 */
-#define LL_PWR_WAKEUP_PIN4                 (PWR_CR3_EWUP4)
-#if defined(PWR_CR3_EWUP5)
-#define LL_PWR_WAKEUP_PIN5                 (PWR_CR3_EWUP5)
-#endif /* PWR_CR3_EWUP5 */
-#define LL_PWR_WAKEUP_PIN6                 (PWR_CR3_EWUP6)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
-  * @{
-  */
-#define LL_PWR_BATTCHARG_RESISTOR_5K       0x000000000u
-#define LL_PWR_BATTCHARG_RESISTOR_1_5K     (PWR_CR4_VBRS)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_GPIO GPIO
-  * @{
-  */
-#define LL_PWR_GPIO_A                      ((uint32_t)(&(PWR->PUCRA)))
-#define LL_PWR_GPIO_B                      ((uint32_t)(&(PWR->PUCRB)))
-#define LL_PWR_GPIO_C                      ((uint32_t)(&(PWR->PUCRC)))
-#define LL_PWR_GPIO_D                      ((uint32_t)(&(PWR->PUCRD)))
-#if defined(GPIOE)
-#define LL_PWR_GPIO_E                      ((uint32_t)(&(PWR->PUCRE)))
-#endif /* GPIOE */
-#define LL_PWR_GPIO_F                      ((uint32_t)(&(PWR->PUCRF)))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
-  * @{
-  */
-#define LL_PWR_GPIO_BIT_0                  0x00000001u
-#define LL_PWR_GPIO_BIT_1                  0x00000002u
-#define LL_PWR_GPIO_BIT_2                  0x00000004u
-#define LL_PWR_GPIO_BIT_3                  0x00000008u
-#define LL_PWR_GPIO_BIT_4                  0x00000010u
-#define LL_PWR_GPIO_BIT_5                  0x00000020u
-#define LL_PWR_GPIO_BIT_6                  0x00000040u
-#define LL_PWR_GPIO_BIT_7                  0x00000080u
-#define LL_PWR_GPIO_BIT_8                  0x00000100u
-#define LL_PWR_GPIO_BIT_9                  0x00000200u
-#define LL_PWR_GPIO_BIT_10                 0x00000400u
-#define LL_PWR_GPIO_BIT_11                 0x00000800u
-#define LL_PWR_GPIO_BIT_12                 0x00001000u
-#define LL_PWR_GPIO_BIT_13                 0x00002000u
-#define LL_PWR_GPIO_BIT_14                 0x00004000u
-#define LL_PWR_GPIO_BIT_15                 0x00008000u
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
-  * @{
-  */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in PWR register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in PWR register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief  Set the main internal regulator output voltage
-  * @rmtoll CR1          VOS           LL_PWR_SetRegulVoltageScaling
-  * @param  VoltageScaling This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
-{
-  MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
-}
-
-/**
-  * @brief  Get the main internal regulator output voltage
-  * @rmtoll CR1          VOS           LL_PWR_GetRegulVoltageScaling
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
-{
-  return (READ_BIT(PWR->CR1, PWR_CR1_VOS));
-}
-
-/**
-  * @brief  Switch the regulator from main mode to low-power mode
-  * @rmtoll CR1          LPR           LL_PWR_EnableLowPowerRunMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_LPR);
-}
-
-/**
-  * @brief  Switch the regulator from low-power mode to main mode
-  * @rmtoll CR1          LPR           LL_PWR_DisableLowPowerRunMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
-}
-
-/**
-  * @brief  Check if the regulator is in low-power mode
-  * @rmtoll CR1          LPR           LL_PWR_IsEnabledLowPowerRunMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Switch from run main mode to run low-power mode.
-  * @rmtoll CR1          LPR           LL_PWR_EnterLowPowerRunMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
-{
-  LL_PWR_EnableLowPowerRunMode();
-}
-
-/**
-  * @brief  Switch from run main mode to low-power mode.
-  * @rmtoll CR1          LPR           LL_PWR_ExitLowPowerRunMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
-{
-  LL_PWR_DisableLowPowerRunMode();
-}
-
-/**
-  * @brief  Enable access to the backup domain
-  * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
-  * @brief  Disable access to the backup domain
-  * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
-}
-
-/**
-  * @brief  Check if the backup domain is enabled
-  * @rmtoll CR1          DBP           LL_PWR_IsEnabledBkUpAccess
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Flash Power-down mode during low power sleep mode
-  * @rmtoll CR1          CFIPD_SLP     LL_PWR_EnableFlashPowerDownInLPSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPSleep(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
-}
-
-/**
-  * @brief  Disable Flash Power-down mode during Low power sleep mode
-  * @rmtoll CR1          CFIPD_SLP     LL_PWR_DisableFlashPowerDownInLPSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPSleep(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP);
-}
-
-/**
-  * @brief  Check if flash power-down mode during low power sleep mode domain is enabled
-  * @rmtoll CR1          CFIPD_SLP     LL_PWR_IsEnableFlashPowerDownInLPSleep
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPSleep(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP) == (PWR_CR1_FPD_LPSLP)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Flash Power-down mode during low power run mode
-  * @rmtoll CR1          CFIPD_RUN     LL_PWR_EnableFlashPowerDownInLPRun
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInLPRun(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
-}
-
-/**
-  * @brief  Disable Flash Power-down mode during Low power run mode
-  * @rmtoll CR1          CFIPD_RUN     LL_PWR_DisableFlashPowerDownInLPRun
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInLPRun(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN);
-}
-
-/**
-  * @brief  Check if flash power-down mode during low power run mode domain is enabled
-  * @rmtoll CR1          CFIPD_RUN     LL_PWR_IsEnableFlashPowerDownInLPRun
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInLPRun(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN) == (PWR_CR1_FPD_LPRUN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Flash Power-down mode during stop mode
-  * @rmtoll CR1          CFIPD_STOP    LL_PWR_EnableFlashPowerDownInStop
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableFlashPowerDownInStop(void)
-{
-  SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
-}
-
-/**
-  * @brief  Disable Flash Power-down mode during stop mode
-  * @rmtoll CR1          CFIPD_STOP    LL_PWR_DisableFlashPowerDownInStop
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableFlashPowerDownInStop(void)
-{
-  CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP);
-}
-
-/**
-  * @brief  Check if flash power-down mode during stop mode domain is enabled
-  * @rmtoll CR1          CFIPD_STOP    LL_PWR_IsEnableFlashPowerDownInStop
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnableFlashPowerDownInStop(void)
-{
-  return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-/**
-  * @brief  Enable VDDIO2 supply
-  * @rmtoll CR2          IOSV          LL_PWR_EnableVddIO2
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableVddIO2(void)
-{
-  SET_BIT(PWR->CR2, PWR_CR2_IOSV);
-}
-
-/**
-  * @brief  Disable VDDIO2 supply
-  * @rmtoll CR2          IOSV          LL_PWR_DisableVddIO2
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableVddIO2(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
-}
-
-/**
-  * @brief  Check if VDDIO2 supply is enabled
-  * @rmtoll CR2          IOSV          LL_PWR_IsEnabledVddIO2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable VDDUSB supply
-  * @rmtoll CR2          USV           LL_PWR_EnableVddUSB
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableVddUSB(void)
-{
-  SET_BIT(PWR->CR2, PWR_CR2_USV);
-}
-
-/**
-  * @brief  Disable VDDUSB supply
-  * @rmtoll CR2          USV           LL_PWR_DisableVddUSB
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableVddUSB(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
-}
-
-/**
-  * @brief  Check if VDDUSB supply is enabled
-  * @rmtoll CR2          USV           LL_PWR_IsEnabledVddUSB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-#if defined (PWR_PVM_SUPPORT)
-/**
-  * @brief  Enable the Power Voltage Monitoring on a peripheral
-  * @rmtoll CR2          PVMUSB         LL_PWR_EnablePVM
-  * @param  PeriphVoltage This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_PVM_USB (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
-{
-  SET_BIT(PWR->CR2, PeriphVoltage);
-}
-
-/**
-  * @brief  Disable the Power Voltage Monitoring on a peripheral
-  * @rmtoll CR2          PVMUSB         LL_PWR_DisablePVM
-  * @param  PeriphVoltage This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_PVM_USB (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
-{
-  CLEAR_BIT(PWR->CR2, PeriphVoltage);
-}
-
-/**
-  * @brief  Check if Power Voltage Monitoring is enabled on a peripheral
-  * @rmtoll CR2          PVMUSB         LL_PWR_IsEnabledPVM
-  * @param  PeriphVoltage This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_PVM_USB (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
-{
-  return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
-}
-#endif /* PWR_PVM_SUPPORT */
-
-/**
-  * @brief  Set Low-Power mode
-  * @rmtoll CR1          LPMS          LL_PWR_SetPowerMode
-  * @param  LowPowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_MODE_STOP0
-  *         @arg @ref LL_PWR_MODE_STOP1
-  *         @arg @ref LL_PWR_MODE_STANDBY
-  *         @arg @ref LL_PWR_MODE_SHUTDOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
-{
-  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
-}
-
-/**
-  * @brief  Get Low-Power mode
-  * @rmtoll CR1          LPMS          LL_PWR_GetPowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_MODE_STOP0
-  *         @arg @ref LL_PWR_MODE_STOP1
-  *         @arg @ref LL_PWR_MODE_STANDBY
-  *         @arg @ref LL_PWR_MODE_SHUTDOWN
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
-}
-
-#if defined (PWR_CR2_PVDE)
-/**
-  * @brief  Configure the high voltage threshold detected by the Power Voltage Detector
-  * @rmtoll CR2          PLS           LL_PWR_SetPVDHighLevel
-  * @param  PVDHighLevel This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_PVDHLEVEL_0
-  *         @arg @ref LL_PWR_PVDHLEVEL_1
-  *         @arg @ref LL_PWR_PVDHLEVEL_2
-  *         @arg @ref LL_PWR_PVDHLEVEL_3
-  *         @arg @ref LL_PWR_PVDHLEVEL_4
-  *         @arg @ref LL_PWR_PVDHLEVEL_5
-  *         @arg @ref LL_PWR_PVDHLEVEL_6
-  *         @arg @ref LL_PWR_PVDHLEVEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPVDHighLevel(uint32_t PVDHighLevel)
-{
-  MODIFY_REG(PWR->CR2, PWR_CR2_PVDRT, PVDHighLevel);
-}
-
-/**
-  * @brief  Get the voltage threshold detection
-  * @rmtoll CR2          PLS           LL_PWR_GetPVDHighLevel
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_PVDHLEVEL_0
-  *         @arg @ref LL_PWR_PVDHLEVEL_1
-  *         @arg @ref LL_PWR_PVDHLEVEL_2
-  *         @arg @ref LL_PWR_PVDHLEVEL_3
-  *         @arg @ref LL_PWR_PVDHLEVEL_4
-  *         @arg @ref LL_PWR_PVDHLEVEL_5
-  *         @arg @ref LL_PWR_PVDHLEVEL_6
-  *         @arg @ref LL_PWR_PVDHLEVEL_7
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDHighLevel(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDRT));
-}
-/**
-  * @brief  Configure the low voltage threshold detected by the Power Voltage Detector
-  * @rmtoll CR2          PLS           LL_PWR_SetPVDLowLevel
-  * @param  PVDLowLevel This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLLEVEL_0
-  *         @arg @ref LL_PWR_PVDLLEVEL_1
-  *         @arg @ref LL_PWR_PVDLLEVEL_2
-  *         @arg @ref LL_PWR_PVDLLEVEL_3
-  *         @arg @ref LL_PWR_PVDLLEVEL_4
-  *         @arg @ref LL_PWR_PVDLLEVEL_5
-  *         @arg @ref LL_PWR_PVDLLEVEL_6
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPVDLowLevel(uint32_t PVDLowLevel)
-{
-  MODIFY_REG(PWR->CR2, PWR_CR2_PVDFT, PVDLowLevel);
-}
-
-/**
-  * @brief  Get the low voltage threshold detection
-  * @rmtoll CR2          PLS           LL_PWR_GetPVDLowLevel
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLLEVEL_0
-  *         @arg @ref LL_PWR_PVDLLEVEL_1
-  *         @arg @ref LL_PWR_PVDLLEVEL_2
-  *         @arg @ref LL_PWR_PVDLLEVEL_3
-  *         @arg @ref LL_PWR_PVDLLEVEL_4
-  *         @arg @ref LL_PWR_PVDLLEVEL_5
-  *         @arg @ref LL_PWR_PVDLLEVEL_6
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLowLevel(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDFT));
-}
-
-/**
-  * @brief  Enable Power Voltage Detector
-  * @rmtoll CR2          PVDE          LL_PWR_EnablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnablePVD(void)
-{
-  SET_BIT(PWR->CR2, PWR_CR2_PVDE);
-}
-
-/**
-  * @brief  Disable Power Voltage Detector
-  * @rmtoll CR2          PVDE          LL_PWR_DisablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisablePVD(void)
-{
-  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
-}
-
-/**
-  * @brief  Check if Power Voltage Detector is enabled
-  * @rmtoll CR2          PVDE          LL_PWR_IsEnabledPVD
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
-{
-  return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR2_PVDE */
-
-/**
-  * @brief  Enable Internal Wake-up line
-  * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableInternWU(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
-}
-
-/**
-  * @brief  Disable Internal Wake-up line
-  * @rmtoll CR3          EIWF          LL_PWR_DisableInternWU
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableInternWU(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
-}
-
-/**
-  * @brief  Check if Internal Wake-up line is enabled
-  * @rmtoll CR3          EIWF          LL_PWR_IsEnabledInternWU
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
-{
-  return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable pull-up and pull-down configuration
-  * @rmtoll CR3          APC           LL_PWR_EnablePUPDCfg
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-/**
-  * @brief  Disable pull-up and pull-down configuration
-  * @rmtoll CR3          APC           LL_PWR_DisablePUPDCfg
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
-}
-
-/**
-  * @brief  Check if pull-up and pull-down configuration  is enabled
-  * @rmtoll CR3          APC           LL_PWR_IsEnabledPUPDCfg
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
-{
-  return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
-}
-
-#if defined(PWR_CR3_RRS)
-/**
-  * @brief  Enable SRAM content retention in Standby mode
-  * @rmtoll CR3          RRS           LL_PWR_EnableSRAMRetention
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableSRAMRetention(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_RRS);
-}
-
-/**
-  * @brief  Disable SRAM content retention in Standby mode
-  * @rmtoll CR3          RRS           LL_PWR_DisableSRAMRetention
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableSRAMRetention(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
-}
-
-/**
-  * @brief  Check if SRAM content retention in Standby mode is enabled
-  * @rmtoll CR3          RRS           LL_PWR_IsEnabledSRAMRetention
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAMRetention(void)
-{
-  return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR3_RRS */
-
-#if defined(PWR_CR3_ENB_ULP)
-/**
-  * @brief  Enable sampling mode of LPMMU reset block
-  * @rmtoll CR3          ENB_ULP       LL_PWR_EnableLPMUResetSamplingMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableLPMUResetSamplingMode(void)
-{
-  SET_BIT(PWR->CR3, PWR_CR3_ENB_ULP);
-}
-
-/**
-  * @brief  Disable sampling mode of LPMMU reset block
-  * @rmtoll CR3          ENB_ULP       LL_PWR_DisableLPMUResetSamplingMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableLPMUResetSamplingMode(void)
-{
-  CLEAR_BIT(PWR->CR3, PWR_CR3_ENB_ULP);
-}
-
-/**
-  * @brief  Check if sampling mode of LPMMU reset block
-  * @rmtoll CR3          ENB_ULP       LL_PWR_IsEnableLPMUResetSamplingMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnableLPMUResetSamplingMode(void)
-{
-  return ((READ_BIT(PWR->CR3, PWR_CR3_ENB_ULP) == (PWR_CR3_ENB_ULP)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR3_ENB_ULP */
-
-/**
-  * @brief  Enable the WakeUp PINx functionality
-  * @rmtoll CR3          EWUP1         LL_PWR_EnableWakeUpPin\n
-  *         CR3          EWUP2         LL_PWR_EnableWakeUpPin\n
-  *         CR3          EWUP3         LL_PWR_EnableWakeUpPin\n
-  *         CR3          EWUP4         LL_PWR_EnableWakeUpPin\n
-  *         CR3          EWUP5         LL_PWR_EnableWakeUpPin\n
-  *         CR3          EWUP6         LL_PWR_EnableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  * @retval None
-  * @note (*) availability depends on devices
-  */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
-{
-  SET_BIT(PWR->CR3, WakeUpPin);
-}
-
-/**
-  * @brief  Disable the WakeUp PINx functionality
-  * @rmtoll CR3          EWUP1         LL_PWR_DisableWakeUpPin\n
-  *         CR3          EWUP2         LL_PWR_DisableWakeUpPin\n
-  *         CR3          EWUP3         LL_PWR_DisableWakeUpPin\n
-  *         CR3          EWUP4         LL_PWR_DisableWakeUpPin\n
-  *         CR3          EWUP5         LL_PWR_DisableWakeUpPin\n
-  *         CR3          EWUP6         LL_PWR_DisableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  * @retval None
-  * @note (*) availability depends on devices
-  */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
-{
-  CLEAR_BIT(PWR->CR3, WakeUpPin);
-}
-
-/**
-  * @brief  Check if the WakeUp PINx functionality is enabled
-  * @rmtoll CR3          EWUP1         LL_PWR_IsEnabledWakeUpPin\n
-  *         CR3          EWUP2         LL_PWR_IsEnabledWakeUpPin\n
-  *         CR3          EWUP3         LL_PWR_IsEnabledWakeUpPin\n
-  *         CR3          EWUP4         LL_PWR_IsEnabledWakeUpPin\n
-  *         CR3          EWUP5         LL_PWR_IsEnabledWakeUpPin\n
-  *         CR3          EWUP6         LL_PWR_IsEnabledWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  * @retval State of bit (1 or 0).
-  * @note (*) availability depends on devices
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
-{
-  return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the resistor impedance
-  * @rmtoll CR4          VBRS          LL_PWR_SetBattChargResistor
-  * @param  Resistor This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_5K
-  *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_1_5K
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
-{
-  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
-}
-
-/**
-  * @brief  Get the resistor impedance
-  * @rmtoll CR4          VBRS          LL_PWR_GetBattChargResistor
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_5K
-  *         @arg @ref LL_PWR_BATTCHARG_RESISTOR_1_5K
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
-}
-
-/**
-  * @brief  Enable battery charging
-  * @rmtoll CR4          VBE           LL_PWR_EnableBatteryCharging
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
-{
-  SET_BIT(PWR->CR4, PWR_CR4_VBE);
-}
-
-/**
-  * @brief  Disable battery charging
-  * @rmtoll CR4          VBE           LL_PWR_DisableBatteryCharging
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
-{
-  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
-}
-
-/**
-  * @brief  Check if battery charging is enabled
-  * @rmtoll CR4          VBE           LL_PWR_IsEnabledBatteryCharging
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
-{
-  return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the Wake-Up pin polarity low for the event detection
-  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityLow\n
-  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityLow\n
-  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityLow\n
-  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityLow\n
-  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityLow\n
-  *         CR4          WP6           LL_PWR_SetWakeUpPinPolarityLow
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  * @retval None
-  * @note (*) availability depends on devices
-  */
-__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
-{
-  SET_BIT(PWR->CR4, WakeUpPin);
-}
-
-/**
-  * @brief  Set the Wake-Up pin polarity high for the event detection
-  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityHigh\n
-  *         CR4          WP6           LL_PWR_SetWakeUpPinPolarityHigh
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  * @note (*) availability depends on devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
-{
-  CLEAR_BIT(PWR->CR4, WakeUpPin);
-}
-
-/**
-  * @brief  Get the Wake-Up pin polarity for the event detection
-  * @rmtoll CR4          WP1           LL_PWR_IsWakeUpPinPolarityLow\n
-  *         CR4          WP2           LL_PWR_IsWakeUpPinPolarityLow\n
-  *         CR4          WP3           LL_PWR_IsWakeUpPinPolarityLow\n
-  *         CR4          WP4           LL_PWR_IsWakeUpPinPolarityLow\n
-  *         CR4          WP5           LL_PWR_IsWakeUpPinPolarityLow\n
-  *         CR4          WP6           LL_PWR_IsWakeUpPinPolarityLow
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN4
-  *         @arg @ref LL_PWR_WAKEUP_PIN5 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN6
-  * @note (*) availability depends on devices
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
-{
-  return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable GPIO pull-up state in Standby and Shutdown modes
-  * @rmtoll PUCRA        PU0-15        LL_PWR_EnableGPIOPullUp\n
-  *         PUCRB        PU0-15        LL_PWR_EnableGPIOPullUp\n
-  *         PUCRC        PU0-15        LL_PWR_EnableGPIOPullUp\n
-  *         PUCRD        PU0-15        LL_PWR_EnableGPIOPullUp\n
-  *         PUCRE        PU0-15        LL_PWR_EnableGPIOPullUp\n
-  *         PUCRF        PU0-13        LL_PWR_EnableGPIOPullUp
-  * @param  GPIO This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_A
-  *         @arg @ref LL_PWR_GPIO_B
-  *         @arg @ref LL_PWR_GPIO_C
-  *         @arg @ref LL_PWR_GPIO_D
-  *         @arg @ref LL_PWR_GPIO_E (*)
-  *         @arg @ref LL_PWR_GPIO_F
-  * @param  GPIONumber This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_BIT_0
-  *         @arg @ref LL_PWR_GPIO_BIT_1
-  *         @arg @ref LL_PWR_GPIO_BIT_2
-  *         @arg @ref LL_PWR_GPIO_BIT_3
-  *         @arg @ref LL_PWR_GPIO_BIT_4
-  *         @arg @ref LL_PWR_GPIO_BIT_5
-  *         @arg @ref LL_PWR_GPIO_BIT_6
-  *         @arg @ref LL_PWR_GPIO_BIT_7
-  *         @arg @ref LL_PWR_GPIO_BIT_8
-  *         @arg @ref LL_PWR_GPIO_BIT_9
-  *         @arg @ref LL_PWR_GPIO_BIT_10
-  *         @arg @ref LL_PWR_GPIO_BIT_11
-  *         @arg @ref LL_PWR_GPIO_BIT_12
-  *         @arg @ref LL_PWR_GPIO_BIT_13
-  *         @arg @ref LL_PWR_GPIO_BIT_14
-  *         @arg @ref LL_PWR_GPIO_BIT_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
-{
-  SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
-}
-
-/**
-  * @brief  Disable GPIO pull-up state in Standby and Shutdown modes
-  * @rmtoll PUCRA        PU0-15        LL_PWR_DisableGPIOPullUp\n
-  *         PUCRB        PU0-15        LL_PWR_DisableGPIOPullUp\n
-  *         PUCRC        PU0-15        LL_PWR_DisableGPIOPullUp\n
-  *         PUCRD        PU0-15        LL_PWR_DisableGPIOPullUp\n
-  *         PUCRE        PU0-15        LL_PWR_DisableGPIOPullUp\n
-  *         PUCRF        PU0-13        LL_PWR_DisableGPIOPullUp
-  * @param  GPIO This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_A
-  *         @arg @ref LL_PWR_GPIO_B
-  *         @arg @ref LL_PWR_GPIO_C
-  *         @arg @ref LL_PWR_GPIO_D
-  *         @arg @ref LL_PWR_GPIO_E (*)
-  *         @arg @ref LL_PWR_GPIO_F
-  * @param  GPIONumber This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_BIT_0
-  *         @arg @ref LL_PWR_GPIO_BIT_1
-  *         @arg @ref LL_PWR_GPIO_BIT_2
-  *         @arg @ref LL_PWR_GPIO_BIT_3
-  *         @arg @ref LL_PWR_GPIO_BIT_4
-  *         @arg @ref LL_PWR_GPIO_BIT_5
-  *         @arg @ref LL_PWR_GPIO_BIT_6
-  *         @arg @ref LL_PWR_GPIO_BIT_7
-  *         @arg @ref LL_PWR_GPIO_BIT_8
-  *         @arg @ref LL_PWR_GPIO_BIT_9
-  *         @arg @ref LL_PWR_GPIO_BIT_10
-  *         @arg @ref LL_PWR_GPIO_BIT_11
-  *         @arg @ref LL_PWR_GPIO_BIT_12
-  *         @arg @ref LL_PWR_GPIO_BIT_13
-  *         @arg @ref LL_PWR_GPIO_BIT_14
-  *         @arg @ref LL_PWR_GPIO_BIT_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
-{
-  CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
-}
-
-/**
-  * @brief  Check if GPIO pull-up state is enabled
-  * @rmtoll PUCRA        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
-  *         PUCRB        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
-  *         PUCRC        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
-  *         PUCRD        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
-  *         PUCRE        PU0-15        LL_PWR_IsEnabledGPIOPullUp\n
-  *         PUCRF        PU0-13        LL_PWR_IsEnabledGPIOPullUp
-  * @param  GPIO This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_A
-  *         @arg @ref LL_PWR_GPIO_B
-  *         @arg @ref LL_PWR_GPIO_C
-  *         @arg @ref LL_PWR_GPIO_D
-  *         @arg @ref LL_PWR_GPIO_E (*)
-  *         @arg @ref LL_PWR_GPIO_F
-  * @param  GPIONumber This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_BIT_0
-  *         @arg @ref LL_PWR_GPIO_BIT_1
-  *         @arg @ref LL_PWR_GPIO_BIT_2
-  *         @arg @ref LL_PWR_GPIO_BIT_3
-  *         @arg @ref LL_PWR_GPIO_BIT_4
-  *         @arg @ref LL_PWR_GPIO_BIT_5
-  *         @arg @ref LL_PWR_GPIO_BIT_6
-  *         @arg @ref LL_PWR_GPIO_BIT_7
-  *         @arg @ref LL_PWR_GPIO_BIT_8
-  *         @arg @ref LL_PWR_GPIO_BIT_9
-  *         @arg @ref LL_PWR_GPIO_BIT_10
-  *         @arg @ref LL_PWR_GPIO_BIT_11
-  *         @arg @ref LL_PWR_GPIO_BIT_12
-  *         @arg @ref LL_PWR_GPIO_BIT_13
-  *         @arg @ref LL_PWR_GPIO_BIT_14
-  *         @arg @ref LL_PWR_GPIO_BIT_15
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
-{
-  return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable GPIO pull-down state in Standby and Shutdown modes
-  * @rmtoll PDCRA        PD0-15        LL_PWR_EnableGPIOPullDown\n
-  *         PDCRB        PD0-15        LL_PWR_EnableGPIOPullDown\n
-  *         PDCRC        PD0-15        LL_PWR_EnableGPIOPullDown\n
-  *         PDCRD        PD0-15        LL_PWR_EnableGPIOPullDown\n
-  *         PDCRE        PD0-15        LL_PWR_EnableGPIOPullDown\n
-  *         PDCRF        PD0-13        LL_PWR_EnableGPIOPullDown
-  * @param  GPIO This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_A
-  *         @arg @ref LL_PWR_GPIO_B
-  *         @arg @ref LL_PWR_GPIO_C
-  *         @arg @ref LL_PWR_GPIO_D
-  *         @arg @ref LL_PWR_GPIO_E (*)
-  *         @arg @ref LL_PWR_GPIO_F
-  * @param  GPIONumber This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_BIT_0
-  *         @arg @ref LL_PWR_GPIO_BIT_1
-  *         @arg @ref LL_PWR_GPIO_BIT_2
-  *         @arg @ref LL_PWR_GPIO_BIT_3
-  *         @arg @ref LL_PWR_GPIO_BIT_4
-  *         @arg @ref LL_PWR_GPIO_BIT_5
-  *         @arg @ref LL_PWR_GPIO_BIT_6
-  *         @arg @ref LL_PWR_GPIO_BIT_7
-  *         @arg @ref LL_PWR_GPIO_BIT_8
-  *         @arg @ref LL_PWR_GPIO_BIT_9
-  *         @arg @ref LL_PWR_GPIO_BIT_10
-  *         @arg @ref LL_PWR_GPIO_BIT_11
-  *         @arg @ref LL_PWR_GPIO_BIT_12
-  *         @arg @ref LL_PWR_GPIO_BIT_13
-  *         @arg @ref LL_PWR_GPIO_BIT_14
-  *         @arg @ref LL_PWR_GPIO_BIT_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
-{
-  SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
-}
-
-/**
-  * @brief  Disable GPIO pull-down state in Standby and Shutdown modes
-  * @rmtoll PDCRA        PD0-15        LL_PWR_DisableGPIOPullDown\n
-  *         PDCRB        PD0-15        LL_PWR_DisableGPIOPullDown\n
-  *         PDCRC        PD0-15        LL_PWR_DisableGPIOPullDown\n
-  *         PDCRD        PD0-15        LL_PWR_DisableGPIOPullDown\n
-  *         PDCRE        PD0-15        LL_PWR_DisableGPIOPullDown\n
-  *         PDCRF        PD0-13        LL_PWR_DisableGPIOPullDown
-  * @param  GPIO This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_A
-  *         @arg @ref LL_PWR_GPIO_B
-  *         @arg @ref LL_PWR_GPIO_C
-  *         @arg @ref LL_PWR_GPIO_D
-  *         @arg @ref LL_PWR_GPIO_E (*)
-  *         @arg @ref LL_PWR_GPIO_F
-  * @param  GPIONumber This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_BIT_0
-  *         @arg @ref LL_PWR_GPIO_BIT_1
-  *         @arg @ref LL_PWR_GPIO_BIT_2
-  *         @arg @ref LL_PWR_GPIO_BIT_3
-  *         @arg @ref LL_PWR_GPIO_BIT_4
-  *         @arg @ref LL_PWR_GPIO_BIT_5
-  *         @arg @ref LL_PWR_GPIO_BIT_6
-  *         @arg @ref LL_PWR_GPIO_BIT_7
-  *         @arg @ref LL_PWR_GPIO_BIT_8
-  *         @arg @ref LL_PWR_GPIO_BIT_9
-  *         @arg @ref LL_PWR_GPIO_BIT_10
-  *         @arg @ref LL_PWR_GPIO_BIT_11
-  *         @arg @ref LL_PWR_GPIO_BIT_12
-  *         @arg @ref LL_PWR_GPIO_BIT_13
-  *         @arg @ref LL_PWR_GPIO_BIT_14
-  *         @arg @ref LL_PWR_GPIO_BIT_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
-{
-  CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
-}
-
-/**
-  * @brief  Check if GPIO pull-down state is enabled
-  * @rmtoll PDCRA        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
-  *         PDCRB        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
-  *         PDCRC        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
-  *         PDCRD        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
-  *         PDCRE        PD0-15        LL_PWR_IsEnabledGPIOPullDown\n
-  *         PDCRF        PD0-13        LL_PWR_IsEnabledGPIOPullDown
-  * @param  GPIO This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_A
-  *         @arg @ref LL_PWR_GPIO_B
-  *         @arg @ref LL_PWR_GPIO_C
-  *         @arg @ref LL_PWR_GPIO_D
-  *         @arg @ref LL_PWR_GPIO_E (*)
-  *         @arg @ref LL_PWR_GPIO_F
-  * @param  GPIONumber This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_GPIO_BIT_0
-  *         @arg @ref LL_PWR_GPIO_BIT_1
-  *         @arg @ref LL_PWR_GPIO_BIT_2
-  *         @arg @ref LL_PWR_GPIO_BIT_3
-  *         @arg @ref LL_PWR_GPIO_BIT_4
-  *         @arg @ref LL_PWR_GPIO_BIT_5
-  *         @arg @ref LL_PWR_GPIO_BIT_6
-  *         @arg @ref LL_PWR_GPIO_BIT_7
-  *         @arg @ref LL_PWR_GPIO_BIT_8
-  *         @arg @ref LL_PWR_GPIO_BIT_9
-  *         @arg @ref LL_PWR_GPIO_BIT_10
-  *         @arg @ref LL_PWR_GPIO_BIT_11
-  *         @arg @ref LL_PWR_GPIO_BIT_12
-  *         @arg @ref LL_PWR_GPIO_BIT_13
-  *         @arg @ref LL_PWR_GPIO_BIT_14
-  *         @arg @ref LL_PWR_GPIO_BIT_15
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
-{
-  return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Internal Wake-up line Flag
-  * @rmtoll SR1          WUFI          LL_PWR_IsActiveFlag_InternWU
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
-{
-  return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Stand-By Flag
-  * @rmtoll SR1          SBF           LL_PWR_IsActiveFlag_SB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
-{
-  return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Wake-up Flag 6
-  * @rmtoll SR1          WUF6          LL_PWR_IsActiveFlag_WU6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
-{
-  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL);
-}
-
-#if defined(PWR_CR3_EWUP5)
-/**
-  * @brief  Get Wake-up Flag 5
-  * @rmtoll SR1          WUF5          LL_PWR_IsActiveFlag_WU5
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
-{
-  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR3_EWUP5 */
-
-/**
-  * @brief  Get Wake-up Flag 4
-  * @rmtoll SR1          WUF4          LL_PWR_IsActiveFlag_WU4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
-{
-  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
-}
-
-#if defined(PWR_CR3_EWUP3)
-/**
-  * @brief  Get Wake-up Flag 3
-  * @rmtoll SR1          WUF3          LL_PWR_IsActiveFlag_WU3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
-{
-  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
-}
-#endif /* PWR_CR3_EWUP3 */
-
-/**
-  * @brief  Get Wake-up Flag 2
-  * @rmtoll SR1          WUF2          LL_PWR_IsActiveFlag_WU2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
-{
-  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get Wake-up Flag 1
-  * @rmtoll SR1          WUF1          LL_PWR_IsActiveFlag_WU1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
-{
-  return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Stand-By Flag
-  * @rmtoll SCR          CSBF          LL_PWR_ClearFlag_SB
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
-{
-  WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
-}
-
-/**
-  * @brief  Clear Wake-up Flags
-  * @rmtoll SCR          CWUF          LL_PWR_ClearFlag_WU
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
-{
-  WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
-}
-
-/**
-  * @brief  Clear Wake-up Flag 6
-  * @rmtoll SCR          CWUF6         LL_PWR_ClearFlag_WU6
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
-{
-  WRITE_REG(PWR->SCR, PWR_SCR_CWUF6);
-}
-
-#if defined(PWR_CR3_EWUP5)
-/**
-  * @brief  Clear Wake-up Flag 5
-  * @rmtoll SCR          CWUF5         LL_PWR_ClearFlag_WU5
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
-{
-  WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
-}
-#endif /* PWR_CR3_EWUP5 */
-
-/**
-  * @brief  Clear Wake-up Flag 4
-  * @rmtoll SCR          CWUF4         LL_PWR_ClearFlag_WU4
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
-{
-  WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
-}
-
-#if defined(PWR_CR3_EWUP3)
-/**
-  * @brief  Clear Wake-up Flag 3
-  * @rmtoll SCR          CWUF3         LL_PWR_ClearFlag_WU3
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
-{
-  WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
-}
-#endif /* PWR_CR3_EWUP3 */
-
-/**
-  * @brief  Clear Wake-up Flag 2
-  * @rmtoll SCR          CWUF2         LL_PWR_ClearFlag_WU2
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
-{
-  WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
-}
-
-/**
-  * @brief  Clear Wake-up Flag 1
-  * @rmtoll SCR          CWUF1         LL_PWR_ClearFlag_WU1
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
-{
-  WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
-}
-
-#if defined (PWR_PVM_SUPPORT)
-/**
-  * @brief  Indicate whether VDD voltage is below or above the selected PVD
-  *         threshold
-  * @rmtoll SR2          PVDMO_USB          LL_PWR_IsActiveFlag_PVMOUSB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB(void)
-{
-  return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_USB) == (PWR_SR2_PVMO_USB)) ? 1UL : 0UL);
-}
-#endif /* PWR_PVM_SUPPORT */
-
-#if defined(PWR_SR2_PVDO)
-/**
-  * @brief  Indicate whether VDD voltage is below or above the selected PVD
-  *         threshold
-  * @rmtoll SR2          PVDO          LL_PWR_IsActiveFlag_PVDO
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
-{
-  return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
-}
-#endif /* PWR_SR2_PVDO */
-
-/**
-  * @brief  Indicate whether the regulator is ready in the selected voltage
-  *         range or if its output voltage is still changing to the required
-  *         voltage level
-  * @note:  Take care, return value "0" means the regulator is ready.
-  *         Return value "1" means the output voltage range is still changing.
-  * @rmtoll SR2          VOSF          LL_PWR_IsActiveFlag_VOS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
-{
-  return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate whether the regulator is ready in main mode or is in
-  *         low-power mode
-  * @note:  Take care, return value "0" means regulator is ready in main mode
-  *         Return value "1" means regulator is in low-power mode (LPR)
-  * @rmtoll SR2          REGLPF        LL_PWR_IsActiveFlag_REGLPF
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
-{
-  return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate whether or not the low-power regulator is ready
-  * @rmtoll SR2          REGLPS        LL_PWR_IsActiveFlag_REGLPS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
-{
-  return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Indicate whether or not the flash is ready to be accessed
-  * @rmtoll SR2          FLASH_RDY     LL_PWR_IsActiveFlag_FLASH_RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASH_RDY(void)
-{
-  return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL);
-}
-
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
-  * @{
-  */
-ErrorStatus LL_PWR_DeInit(void);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(PWR) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h

@@ -1,3886 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_rcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_RCC_H
-#define STM32G0xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Variables RCC Private Variables
-  * @{
-  */
-
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
-  * @{
-  */
-
-/**
-  * @brief  RCC Clocks Frequency Structure
-  */
-typedef struct
-{
-  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
-  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
-  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
-} LL_RCC_ClocksTypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
-  * @brief    Defines used to adapt values of different oscillators
-  * @note     These values could be modified in the user environment according to
-  *           HW set-up.
-  * @{
-  */
-#if !defined  (HSE_VALUE)
-#define HSE_VALUE    8000000U   /*!< Value of the HSE oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined  (LSE_VALUE)
-#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSI_VALUE)
-#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-#define EXTERNAL_CLOCK_VALUE    48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-#if defined(RCC_HSI48_SUPPORT)
-#if !defined  (HSI48_VALUE)
-#define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
-#endif /* HSI48_VALUE */
-#endif /* RCC_HSI48_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
-  * @{
-  */
-#define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
-#define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
-#define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */
-#define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */
-#if defined(RCC_HSI48_SUPPORT)
-#define LL_RCC_CICR_HSI48RDYC              RCC_CICR_HSI48RDYC   /*!< HSI48 Ready Interrupt Clear */
-#endif /* RCC_HSI48_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
-  * @{
-  */
-#define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF     /*!< LSI Ready Interrupt flag */
-#define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */
-#if defined(RCC_HSI48_SUPPORT)
-#define LL_RCC_CIFR_HSI48RDYF              RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */
-#endif /* RCC_HSI48_SUPPORT */
-#define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */
-#define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */
-#define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
-#define LL_RCC_CSR_OBLRSTF                 RCC_CSR_OBLRSTF    /*!< OBL reset flag */
-#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
-#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
-#define LL_RCC_CSR_PWRRSTF                 RCC_CSR_PWRRSTF    /*!< BOR or POR/PDR reset flag */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
-  * @{
-  */
-#define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
-#if defined(RCC_HSI48_SUPPORT)
-#define LL_RCC_CIER_HSI48RDYIE             RCC_CIER_HSI48RDYIE    /*!< HSI48 Ready Interrupt Enable */
-#endif /* RCC_HSI48_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
-  * @{
-  */
-#define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving capability */
-#define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium low driving capability */
-#define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium high driving capability */
-#define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE  LSCO Selection
-  * @{
-  */
-#define LL_RCC_LSCO_CLKSOURCE_LSI          0x00000000U                 /*!< LSI selection for low speed clock  */
-#define LL_RCC_LSCO_CLKSOURCE_LSE          RCC_BDCR_LSCOSEL            /*!< LSE selection for low speed clock  */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_HSI           0x00000000U                        /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_0                      /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_1                      /*!< PLL selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_LSI           (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)    /*!< LSI selection used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_LSE           RCC_CFGR_SW_2                      /*!< LSE selection used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    0x00000000U                         /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_0                      /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_1                      /*!< PLL used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_LSI    (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)   /*!< LSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_LSE    RCC_CFGR_SWS_2                      /*!< LSE used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
-  * @{
-  */
-#define LL_RCC_SYSCLK_DIV_1                0x00000000U                                                             /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_3                                                         /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4                (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0)                                     /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8                (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1)                                     /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16               (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0)                   /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64               (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2)                                     /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0)                   /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1)                   /*!< SYSCLK divided by 256 */
-#define LL_RCC_SYSCLK_DIV_512              (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
-  * @{
-  */
-#define LL_RCC_APB1_DIV_1                  0x00000000U                                           /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE_2                                       /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4                  (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0)                   /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8                  (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1)                   /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16                 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_HSI_DIV  HSI division factor
-  * @{
-  */
-#define LL_RCC_HSI_DIV_1                  0x00000000U                                /*!< HSI not divided */
-#define LL_RCC_HSI_DIV_2                  RCC_CR_HSIDIV_0                            /*!< HSI divided by 2 */
-#define LL_RCC_HSI_DIV_4                  RCC_CR_HSIDIV_1                            /*!< HSI divided by 4 */
-#define LL_RCC_HSI_DIV_8                  (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)        /*!< HSI divided by 8 */
-#define LL_RCC_HSI_DIV_16                 RCC_CR_HSIDIV_2                            /*!< HSI divided by 16 */
-#define LL_RCC_HSI_DIV_32                 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0)        /*!< HSI divided by 32 */
-#define LL_RCC_HSI_DIV_64                 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1)        /*!< HSI divided by 64 */
-#define LL_RCC_HSI_DIV_128                RCC_CR_HSIDIV                              /*!< HSI divided by 128 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
-  * @{
-  */
-#define LL_RCC_MCO1SOURCE_NOCLOCK          0x00000000U                            /*!< MCO output disabled, no clock on MCO */
-#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
-#if defined(RCC_HSI48_SUPPORT)
-#define LL_RCC_MCO1SOURCE_HSI48            RCC_CFGR_MCOSEL_1                      /*!< HSI48 selection as MCO1 source */
-#endif /* RCC_HSI48_SUPPORT */
-#define LL_RCC_MCO1SOURCE_HSI              (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< Main PLL selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_LSI              (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_LSE              (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
-#if defined(RCC_CFGR_MCOSEL_3)
-#define LL_RCC_MCO1SOURCE_PLLPCLK         RCC_CFGR_MCOSEL_3                       /*!< PLLPCLK selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_PLLQCLK         (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0)   /*!< PLLQCLK selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_RTCCLK          (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1)   /*!< RTCCLK selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_RTC_WKUP        (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */
-#endif /* RCC_CFGR_MCOSEL_3 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
-  * @{
-  */
-#define LL_RCC_MCO1_DIV_1                  0x00000000U                                                 /*!< MCO1 not divided */
-#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_0                                           /*!< MCO1 divided by 2 */
-#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_1                                           /*!< MCO1 divided by 4 */
-#define LL_RCC_MCO1_DIV_8                  (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0)                     /*!< MCO1 divided by 8 */
-#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_2                                           /*!< MCO1 divided by 16 */
-#define LL_RCC_MCO1_DIV_32                 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0)                     /*!< MCO1 divided by 32 */
-#define LL_RCC_MCO1_DIV_64                 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1)                     /*!< MCO1 divided by 64 */
-#define LL_RCC_MCO1_DIV_128                (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */
-#if defined(RCC_CFGR_MCOPRE_3)
-#define LL_RCC_MCO1_DIV_256                 RCC_CFGR_MCOPRE_3                                           /*!< MCO divided by 256 */
-#define LL_RCC_MCO1_DIV_512                (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0)                      /*!< MCO divided by 512 */
-#define LL_RCC_MCO1_DIV_1024               (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1)                      /*!< MCO divided by 1024 */
-#endif /* RCC_CFGR_MCOPRE_3 */
-/**
-  * @}
-  */
-
-#if defined(RCC_MCO2_SUPPORT)
-/** @defgroup RCC_LL_EC_MCO2SOURCE  MCO2 SOURCE selection
-  * @{
-  */
-#define LL_RCC_MCO2SOURCE_NOCLOCK          0x00000000U                                                    /*!< MCO output disabled, no clock on MCO */
-#define LL_RCC_MCO2SOURCE_SYSCLK           RCC_CFGR_MCO2SEL_0                                             /*!< SYSCLK selection as MCO2 source */
-#if defined(RCC_HSI48_SUPPORT)
-#define LL_RCC_MCO2SOURCE_HSI48            RCC_CFGR_MCO2SEL_1                                             /*!< HSI48 selection as MCO2 source */
-#endif /* RCC_HSI48_SUPPORT */
-#define LL_RCC_MCO2SOURCE_HSI              (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)                      /*!< HSI16 selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_HSE              RCC_CFGR_MCO2SEL_2                                             /*!< HSE selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_PLLCLK           (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0)                      /*!< Main PLL "R" clock selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_LSI              (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1)                      /*!< LSI selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_LSE              (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_PLLPCLK          RCC_CFGR_MCO2SEL_3                                             /*!< PLL "P" clock selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_PLLQCLK          (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0)                      /*!< PLL "Q" clock  selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_RTCCLK           (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1)                      /*!< RTC Clock selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_RTC_WKUP         (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< RTC Wakeup timer selection as MCO2 source */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCO2_DIV  MCO2 prescaler
-  * @{
-  */
-#define LL_RCC_MCO2_DIV_1                  0x00000000U                                                    /*!< MCO2 not divided */
-#define LL_RCC_MCO2_DIV_2                  RCC_CFGR_MCO2PRE_0                                             /*!< MCO2 divided by 2 */
-#define LL_RCC_MCO2_DIV_4                  RCC_CFGR_MCO2PRE_1                                             /*!< MCO2 divided by 4 */
-#define LL_RCC_MCO2_DIV_8                  (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0)                      /*!< MCO2 divided by 8 */
-#define LL_RCC_MCO2_DIV_16                 RCC_CFGR_MCO2PRE_2                                             /*!< MCO2 divided by 16 */
-#define LL_RCC_MCO2_DIV_32                 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0)                      /*!< MCO2 divided by 32 */
-#define LL_RCC_MCO2_DIV_64                 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1)                      /*!< MCO2 divided by 64 */
-#define LL_RCC_MCO2_DIV_128                (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */
-#define LL_RCC_MCO2_DIV_256                RCC_CFGR_MCO2PRE_3                                             /*!< MCO2 divided by 256 */
-#define LL_RCC_MCO2_DIV_512                (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0)                      /*!< MCO2 divided by 512 */
-#define LL_RCC_MCO2_DIV_1024               (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1)                      /*!< MCO2 divided by 1024 */
-/**
-  * @}
-  */
-#endif /* RCC_MCO2_SUPPORT */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
-  * @{
-  */
-#define LL_RCC_PERIPH_FREQUENCY_NO        0x00000000U                 /*!< No clock enabled for the peripheral            */
-#define LL_RCC_PERIPH_FREQUENCY_NA        0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
-  * @{
-  */
-#define LL_RCC_USART1_CLKSOURCE_PCLK1      ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U)            /*!< PCLK1 clock used as USART1 clock source */
-#define LL_RCC_USART1_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0)  /*!< SYSCLK clock used as USART1 clock source */
-#define LL_RCC_USART1_CLKSOURCE_HSI        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1)  /*!< HSI clock used as USART1 clock source */
-#define LL_RCC_USART1_CLKSOURCE_LSE        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)    /*!< LSE clock used as USART1 clock source */
-#define LL_RCC_USART2_CLKSOURCE_PCLK1      ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U)            /*!< PCLK1 clock used as USART2 clock source */
-#define LL_RCC_USART2_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0)  /*!< SYSCLK clock used as USART2 clock source */
-#define LL_RCC_USART2_CLKSOURCE_HSI        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1)  /*!< HSI clock used as USART2 clock source */
-#define LL_RCC_USART2_CLKSOURCE_LSE        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)    /*!< LSE clock used as USART2 clock source */
-#if defined(RCC_CCIPR_USART3SEL)
-#define LL_RCC_USART3_CLKSOURCE_PCLK1      ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U)           /*!< PCLK1 clock used as USART3 clock source */
-#define LL_RCC_USART3_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
-#define LL_RCC_USART3_CLKSOURCE_HSI        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
-#define LL_RCC_USART3_CLKSOURCE_LSE        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)   /*!< LSE clock used as USART3 clock source */
-#endif /* RCC_CCIPR_USART3SEL */
-/**
-  * @}
-  */
-
-#if defined(LPUART1) || defined(LPUART2)
-/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
-  * @{
-  */
-#if defined(LPUART2)
-#define LL_RCC_LPUART2_CLKSOURCE_PCLK1     ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U)              /*!< PCLK1 clock used as LPUART2 clock source */
-#define LL_RCC_LPUART2_CLKSOURCE_SYSCLK    ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0)  /*!< SYSCLK clock used as LPUART2 clock source */
-#define LL_RCC_LPUART2_CLKSOURCE_HSI       ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1)  /*!< HSI clock used as LPUART2 clock source */
-#define LL_RCC_LPUART2_CLKSOURCE_LSE       ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL)    /*!< LSE clock used as LPUART2 clock source */
-#endif /* LPUART2 */
-#define LL_RCC_LPUART1_CLKSOURCE_PCLK1     ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U)              /*!< PCLK1 clock used as LPUART1 clock source */
-#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0)   /*!< SYSCLK clock used as LPUART1 clock source */
-#define LL_RCC_LPUART1_CLKSOURCE_HSI       ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1)   /*!< HSI clock used as LPUART1 clock source */
-#define LL_RCC_LPUART1_CLKSOURCE_LSE       ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL)     /*!< LSE clock used as LPUART1 clock source */
-/**
-  * @}
-  */
-#endif /* LPUART1 || LPUART2 */
-
-/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
-  * @{
-  */
-#define LL_RCC_I2C1_CLKSOURCE_PCLK1        ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U)          /*!< PCLK1 clock used as I2C1 clock source */
-#define LL_RCC_I2C1_CLKSOURCE_SYSCLK       ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0)  /*!< SYSCLK clock used as I2C1 clock source */
-#define LL_RCC_I2C1_CLKSOURCE_HSI          ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1)  /*!< HSI clock used as I2C1 clock source */
-#if defined(RCC_CCIPR_I2C2SEL)
-#define LL_RCC_I2C2_CLKSOURCE_PCLK1        ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U)          /*!< PCLK1 clock used as I2C2 clock source */
-#define LL_RCC_I2C2_CLKSOURCE_SYSCLK       ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0)  /*!< SYSCLK clock used as I2C2 clock source */
-#define LL_RCC_I2C2_CLKSOURCE_HSI          ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1)  /*!< HSI clock used as I2C2 clock source */
-#endif /* RCC_CCIPR_I2C2SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_I2Sx_CLKSOURCE Peripheral I2S clock source selection
-  * @{
-  */
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define LL_RCC_I2S1_CLKSOURCE_SYSCLK      ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U)          /*!< SYSCLK clock used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_PLL         ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0)  /*!< PLL clock used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_HSI         ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1)  /*!< HSI clock used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_PIN         ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL)    /*!< External clock used as I2S1 clock source */
-#define LL_RCC_I2S2_CLKSOURCE_SYSCLK      ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U)          /*!< SYSCLK clock used as I2S2 clock source */
-#define LL_RCC_I2S2_CLKSOURCE_PLL         ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0)  /*!< PLL clock used as I2S2 clock source */
-#define LL_RCC_I2S2_CLKSOURCE_HSI         ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1)  /*!< HSI clock used as I2S2 clock source */
-#define LL_RCC_I2S2_CLKSOURCE_PIN         ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL)    /*!< External clock used as I2S2 clock source */
-#else
-#define LL_RCC_I2S1_CLKSOURCE_SYSCLK      0x00000000U                  /*!< SYSCLK clock used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_PLL         RCC_CCIPR_I2S1SEL_0          /*!< PLL clock used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_HSI         RCC_CCIPR_I2S1SEL_1          /*!< HSI clock used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_PIN         RCC_CCIPR_I2S1SEL            /*!< External clock used as I2S1 clock source */
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-/**
-  * @}
-  */
-
-#if defined(RCC_CCIPR_TIM1SEL)
-/** @defgroup RCC_LL_EC_TIMx_CLKSOURCE Peripheral TIM clock source selection
-  * @{
-  */
-#define LL_RCC_TIM1_CLKSOURCE_PCLK1        (RCC_CCIPR_TIM1SEL   | (0x00000000U >> 16U))          /*!< PCLK1 clock used as TIM1 clock source */
-#define LL_RCC_TIM1_CLKSOURCE_PLL          (RCC_CCIPR_TIM1SEL   | (RCC_CCIPR_TIM1SEL >> 16U))    /*!< PLL used as TIM1 clock source */
-/**
-  * @}
-  */
-#endif /* RCC_CCIPR_TIM1SEL */
-
-#if defined(RCC_CCIPR_TIM15SEL)
-/** @addtogroup RCC_LL_EC_TIMx_CLKSOURCE
-  * @{
-  */
-#define LL_RCC_TIM15_CLKSOURCE_PCLK1       (RCC_CCIPR_TIM15SEL  | (0x00000000U >> 16U))          /*!< PCLK1 clock used as TIM15 clock source */
-#define LL_RCC_TIM15_CLKSOURCE_PLL         (RCC_CCIPR_TIM15SEL  | (RCC_CCIPR_TIM15SEL >> 16U))   /*!< PLL used as TIM15 clock source */
-/**
-  * @}
-  */
-#endif /* RCC_CCIPR_TIM15SEL */
-
-#if defined(LPTIM1) && defined(LPTIM2)
-/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
-  * @{
-  */
-#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U))           /*!< PCLK1 selected as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSI        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_HSI        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI selected as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSE        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U))   /*!< LSE selected as LPTIM1 clock */
-#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1      (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U))           /*!< PCLK1 selected as LPTIM2 clock */
-#define LL_RCC_LPTIM2_CLKSOURCE_LSI        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI selected as LPTIM2 clock */
-#define LL_RCC_LPTIM2_CLKSOURCE_HSI        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI selected as LPTIM2 clock */
-#define LL_RCC_LPTIM2_CLKSOURCE_LSE        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U))   /*!< LSE selected as LPTIM2 clock */
-/**
-  * @}
-  */
-#endif /* LPTIM1 && LPTIM2*/
-
-#if defined(CEC)
-/** @defgroup RCC_LL_EC_CEC_CLKSOURCE_HSI Peripheral CEC clock source selection
-  * @{
-  */
-#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488    0x00000000U                   /*!< HSI oscillator clock divided by 488 used as CEC clock */
-#define LL_RCC_CEC_CLKSOURCE_LSE           RCC_CCIPR_CECSEL              /*!< LSE oscillator clock used as CEC clock */
-
-/**
-  * @}
-  */
-#endif /* CEC */
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE_HSI Peripheral FDCAN clock source selection
-  * @{
-  */
-#define LL_RCC_FDCAN_CLKSOURCE_PCLK1         0x00000000U                   /*!< PCLK1 oscillator clock used as FDCAN clock */
-#define LL_RCC_FDCAN_CLKSOURCE_PLL           RCC_CCIPR2_FDCANSEL_0          /*!< PLL "Q"  oscillator clock used as FDCAN clock */
-#define LL_RCC_FDCAN_CLKSOURCE_HSE           RCC_CCIPR2_FDCANSEL_1          /*!< HSE oscillator clock used as FDCAN clock */
-
-/**
-  * @}
-  */
-#endif /* FDCAN1 || FDCAN2 */
-
-#if defined(RNG)
-/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
-  * @{
-  */
-#define LL_RCC_RNG_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RNG clock */
-#define LL_RCC_RNG_CLKSOURCE_HSI_DIV8      RCC_CCIPR_RNGSEL_0            /*!< HSI oscillator clock divided by 8 used as RNG clock, available on cut2.0 */
-#define LL_RCC_RNG_CLKSOURCE_SYSCLK        RCC_CCIPR_RNGSEL_1            /*!< SYSCLK divided by 1 used as RNG clock */
-#define LL_RCC_RNG_CLKSOURCE_PLL           RCC_CCIPR_RNGSEL              /*!< PLL used as RNG clock */
-/**
-  * @}
-  */
-#endif /* RNG */
-
-#if defined(RNG)
-/** @defgroup RCC_LL_EC_RNG_CLK_DIV Peripheral RNG clock division factor
-  * @{
-  */
-#define LL_RCC_RNG_CLK_DIV1                0x00000000U                    /*!< RNG clock not divided  */
-#define LL_RCC_RNG_CLK_DIV2                RCC_CCIPR_RNGDIV_0             /*!< RNG clock divided by 2 */
-#define LL_RCC_RNG_CLK_DIV4                RCC_CCIPR_RNGDIV_1             /*!< RNG clock divided by 4 */
-#define LL_RCC_RNG_CLK_DIV8                RCC_CCIPR_RNGDIV               /*!< RNG clock divided by 8 */
-/**
-  * @}
-  */
-#endif /* RNG */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
-  * @{
-  */
-#if defined(RCC_HSI48_SUPPORT)
-#define LL_RCC_USB_CLKSOURCE_HSI48         0x00000000U            /*!< HSI48 clock used as USB clock source */
-#endif /* RCC_HSI48_SUPPORT */
-#define LL_RCC_USB_CLKSOURCE_HSE           RCC_CCIPR2_USBSEL_0  /*!< PLL clock used as USB clock source */
-#define LL_RCC_USB_CLKSOURCE_PLL           RCC_CCIPR2_USBSEL_1  /*!< PLL clock used as USB clock source */
-/**
-  * @}
-  */
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
-  * @{
-  */
-#define LL_RCC_ADC_CLKSOURCE_SYSCLK        0x00000000U                   /*!< SYSCLK used as ADC clock */
-#define LL_RCC_ADC_CLKSOURCE_PLL           RCC_CCIPR_ADCSEL_0            /*!< PLL used as ADC clock */
-#define LL_RCC_ADC_CLKSOURCE_HSI           RCC_CCIPR_ADCSEL_1            /*!< HSI used as ADC clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source
-  * @{
-  */
-#define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
-#define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
-#if defined(RCC_CCIPR_USART3SEL)
-#define LL_RCC_USART3_CLKSOURCE            RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
-#endif /* RCC_CCIPR_USART3SEL */
-/**
-  * @}
-  */
-
-#if defined(LPUART1)
-/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
-  * @{
-  */
-#define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
-#if defined(LPUART2)
-#define LL_RCC_LPUART2_CLKSOURCE           RCC_CCIPR_LPUART2SEL /*!< LPUART2 Clock source selection */
-#endif /* LPUART2 */
-/**
-  * @}
-  */
-#endif /* LPUART1 */
-
-/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
-  * @{
-  */
-#define LL_RCC_I2C1_CLKSOURCE              RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */
-#if defined(RCC_CCIPR_I2C2SEL)
-#define LL_RCC_I2C2_CLKSOURCE              RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */
-#endif /* RCC_CCIPR_I2C2SEL */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
-  * @{
-  */
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define LL_RCC_I2S1_CLKSOURCE              RCC_CCIPR2_I2S1SEL /*!< I2S1 Clock source selection */
-#define LL_RCC_I2S2_CLKSOURCE              RCC_CCIPR2_I2S2SEL /*!< I2S2 Clock source selection */
-#else
-#define LL_RCC_I2S1_CLKSOURCE              RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-/**
-  * @}
-  */
-
-#if defined(RCC_CCIPR_TIM1SEL)
-/** @defgroup RCC_LL_EC_TIMx Peripheral TIMx get clock source
-  * @{
-  */
-#define LL_RCC_TIM1_CLKSOURCE              RCC_CCIPR_TIM1SEL   /*!< TIM1 Clock source selection */
-#if defined(RCC_CCIPR_TIM15SEL)
-#define LL_RCC_TIM15_CLKSOURCE             RCC_CCIPR_TIM15SEL  /*!< TIM15 Clock source selection */
-#endif /* RCC_CCIPR_TIM15SEL */
-/**
-  * @}
-  */
-#endif /* RCC_CCIPR_TIM1SEL */
-
-#if defined(LPTIM1) && defined(LPTIM2)
-/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
-  * @{
-  */
-#define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL /*!< LPTIM2 Clock source selection */
-#define LL_RCC_LPTIM2_CLKSOURCE            RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */
-/**
-  * @}
-  */
-#endif /* LPTIM1 && LPTIM2 */
-
-#if defined(CEC)
-/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
-  * @{
-  */
-#define LL_RCC_CEC_CLKSOURCE               RCC_CCIPR_CECSEL        /*!< CEC Clock source selection */
-/**
-  * @}
-  */
-#endif /* CEC */
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
-  * @{
-  */
-#define LL_RCC_FDCAN_CLKSOURCE               RCC_CCIPR2_FDCANSEL        /*!< FDCAN Clock source selection */
-/**
-  * @}
-  */
-#endif /* FDCAN1 */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
-  * @{
-  */
-#define LL_RCC_USB_CLKSOURCE               RCC_CCIPR2_USBSEL /*!< USB Clock source selection */
-/**
-  * @}
-  */
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-#if defined(RNG)
-/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
-  * @{
-  */
-#define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_RNGSEL        /*!< RNG Clock source selection */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_RNG_DIV Peripheral RNG get clock division factor
-  * @{
-  */
-#define LL_RCC_RNG_CLKDIV                  RCC_CCIPR_RNGDIV        /*!< RNG Clock division factor */
-/**
-  * @}
-  */
-#endif /* RNG */
-
-/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
-  * @{
-  */
-#define LL_RCC_ADC_CLKSOURCE               RCC_CCIPR_ADCSEL        /*!< ADC Clock source selection */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
-  * @{
-  */
-#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_LL_EC_PLLSOURCE  PLL entry clock source
-  * @{
-  */
-#define LL_RCC_PLLSOURCE_NONE              0x00000000U             /*!< No clock */
-#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLM_DIV  PLL division factor (PLLM)
-  * @{
-  */
-#define LL_RCC_PLLM_DIV_1                  0x00000000U                                 /*!< PLL division factor by 1 */
-#define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_0)                        /*!< PLL division factor by 2 */
-#define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1)                        /*!< PLL division factor by 3 */
-#define LL_RCC_PLLM_DIV_4                  ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 4 */
-#define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2)                        /*!< PLL division factor by 5 */
-#define LL_RCC_PLLM_DIV_6                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 6 */
-#define LL_RCC_PLLM_DIV_7                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL division factor by 7 */
-#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM)                          /*!< PLL division factor by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
-  * @{
-  */
-#define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_0)                     /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
-#define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
-#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
-#define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
-#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
-#define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
-#define LL_RCC_PLLR_DIV_8                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
-  * @{
-  */
-#define LL_RCC_PLLP_DIV_2                  (RCC_PLLCFGR_PLLP_0)                                              /*!< Main PLL division factor for PLLP output by 2 */
-#define LL_RCC_PLLP_DIV_3                  (RCC_PLLCFGR_PLLP_1)                                              /*!< Main PLL division factor for PLLP output by 3 */
-#define LL_RCC_PLLP_DIV_4                  (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1)                           /*!< Main PLL division factor for PLLP output by 4 */
-#define LL_RCC_PLLP_DIV_5                  (RCC_PLLCFGR_PLLP_2)                                              /*!< Main PLL division factor for PLLP output by 5 */
-#define LL_RCC_PLLP_DIV_6                  (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2)                           /*!< Main PLL division factor for PLLP output by 6 */
-#define LL_RCC_PLLP_DIV_7                  (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)                           /*!< Main PLL division factor for PLLP output by 7 */
-#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2)        /*!< Main PLL division factor for PLLP output by 8 */
-#define LL_RCC_PLLP_DIV_9                  (RCC_PLLCFGR_PLLP_3)                                              /*!< Main PLL division factor for PLLP output by 9 */
-#define LL_RCC_PLLP_DIV_10                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3)                           /*!< Main PLL division factor for PLLP output by 10 */
-#define LL_RCC_PLLP_DIV_11                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)                           /*!< Main PLL division factor for PLLP output by 11 */
-#define LL_RCC_PLLP_DIV_12                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3)        /*!< Main PLL division factor for PLLP output by 12 */
-#define LL_RCC_PLLP_DIV_13                 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)                           /*!< Main PLL division factor for PLLP output by 13 */
-#define LL_RCC_PLLP_DIV_14                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)        /*!< Main PLL division factor for PLLP output by 14 */
-#define LL_RCC_PLLP_DIV_15                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)        /*!< Main PLL division factor for PLLP output by 15 */
-#define LL_RCC_PLLP_DIV_16                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
-#define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLP_4)                                              /*!< Main PLL division factor for PLLP output by 17 */
-#define LL_RCC_PLLP_DIV_18                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 18 */
-#define LL_RCC_PLLP_DIV_19                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 19 */
-#define LL_RCC_PLLP_DIV_20                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 20 */
-#define LL_RCC_PLLP_DIV_21                 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 21 */
-#define LL_RCC_PLLP_DIV_22                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 22 */
-#define LL_RCC_PLLP_DIV_23                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 23 */
-#define LL_RCC_PLLP_DIV_24                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
-#define LL_RCC_PLLP_DIV_25                 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)                           /*!< Main PLL division factor for PLLP output by 25 */
-#define LL_RCC_PLLP_DIV_26                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 26 */
-#define LL_RCC_PLLP_DIV_27                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 27*/
-#define LL_RCC_PLLP_DIV_28                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
-#define LL_RCC_PLLP_DIV_29                 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)        /*!< Main PLL division factor for PLLP output by 29 */
-#define LL_RCC_PLLP_DIV_30                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
-#define LL_RCC_PLLP_DIV_31                 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
-#define LL_RCC_PLLP_DIV_32                 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
-/**
-  * @}
-  */
-
-#if defined(RCC_PLLQ_SUPPORT)
-/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
-  * @{
-  */
-#define LL_RCC_PLLQ_DIV_2                  (RCC_PLLCFGR_PLLQ_0)                    /*!< Main PLL division factor for PLLQ output by 2 */
-#define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1)                    /*!< Main PLL division factor for PLLQ output by 3 */
-#define LL_RCC_PLLQ_DIV_4                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
-#define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2)                    /*!< Main PLL division factor for PLLQ output by 5 */
-#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
-#define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
-#define LL_RCC_PLLQ_DIV_8                  (RCC_PLLCFGR_PLLQ)                      /*!< Main PLL division factor for PLLQ output by 8 */
-/**
-  * @}
-  */
-#endif /* RCC_PLLQ_SUPPORT */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in RCC register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__))
-
-/**
-  * @brief  Read a value in RCC register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to calculate the PLLCLK frequency on system domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
-  * @param  __PLLR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  *         @arg @ref LL_RCC_PLLR_DIV_8
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__)   \
-  ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
-   (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))
-
-/**
-  * @brief  Helper macro to calculate the PLLPCLK frequency used on I2S domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
-  * @param  __PLLP__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_3
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_5
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_7
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  *         @arg @ref LL_RCC_PLLP_DIV_9
-  *         @arg @ref LL_RCC_PLLP_DIV_10
-  *         @arg @ref LL_RCC_PLLP_DIV_11
-  *         @arg @ref LL_RCC_PLLP_DIV_12
-  *         @arg @ref LL_RCC_PLLP_DIV_13
-  *         @arg @ref LL_RCC_PLLP_DIV_14
-  *         @arg @ref LL_RCC_PLLP_DIV_15
-  *         @arg @ref LL_RCC_PLLP_DIV_16
-  *         @arg @ref LL_RCC_PLLP_DIV_17
-  *         @arg @ref LL_RCC_PLLP_DIV_18
-  *         @arg @ref LL_RCC_PLLP_DIV_19
-  *         @arg @ref LL_RCC_PLLP_DIV_20
-  *         @arg @ref LL_RCC_PLLP_DIV_21
-  *         @arg @ref LL_RCC_PLLP_DIV_22
-  *         @arg @ref LL_RCC_PLLP_DIV_23
-  *         @arg @ref LL_RCC_PLLP_DIV_24
-  *         @arg @ref LL_RCC_PLLP_DIV_25
-  *         @arg @ref LL_RCC_PLLP_DIV_26
-  *         @arg @ref LL_RCC_PLLP_DIV_27
-  *         @arg @ref LL_RCC_PLLP_DIV_28
-  *         @arg @ref LL_RCC_PLLP_DIV_29
-  *         @arg @ref LL_RCC_PLLP_DIV_30
-  *         @arg @ref LL_RCC_PLLP_DIV_31
-  *         @arg @ref LL_RCC_PLLP_DIV_32
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)  \
-  ((__INPUTFREQ__)  * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
-   (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
-
-#if defined(RCC_CCIPR2_I2S2SEL)
-/**
-  * @brief  Helper macro to calculate the PLLPCLK frequency used on I2S2 domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
-  * @param  __PLLP__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_3
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_5
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_7
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  *         @arg @ref LL_RCC_PLLP_DIV_9
-  *         @arg @ref LL_RCC_PLLP_DIV_10
-  *         @arg @ref LL_RCC_PLLP_DIV_11
-  *         @arg @ref LL_RCC_PLLP_DIV_12
-  *         @arg @ref LL_RCC_PLLP_DIV_13
-  *         @arg @ref LL_RCC_PLLP_DIV_14
-  *         @arg @ref LL_RCC_PLLP_DIV_15
-  *         @arg @ref LL_RCC_PLLP_DIV_16
-  *         @arg @ref LL_RCC_PLLP_DIV_17
-  *         @arg @ref LL_RCC_PLLP_DIV_18
-  *         @arg @ref LL_RCC_PLLP_DIV_19
-  *         @arg @ref LL_RCC_PLLP_DIV_20
-  *         @arg @ref LL_RCC_PLLP_DIV_21
-  *         @arg @ref LL_RCC_PLLP_DIV_22
-  *         @arg @ref LL_RCC_PLLP_DIV_23
-  *         @arg @ref LL_RCC_PLLP_DIV_24
-  *         @arg @ref LL_RCC_PLLP_DIV_25
-  *         @arg @ref LL_RCC_PLLP_DIV_26
-  *         @arg @ref LL_RCC_PLLP_DIV_27
-  *         @arg @ref LL_RCC_PLLP_DIV_28
-  *         @arg @ref LL_RCC_PLLP_DIV_29
-  *         @arg @ref LL_RCC_PLLP_DIV_30
-  *         @arg @ref LL_RCC_PLLP_DIV_31
-  *         @arg @ref LL_RCC_PLLP_DIV_32
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)  \
-  ((__INPUTFREQ__)  * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
-   (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
-#endif /* RCC_CCIPR2_I2S2SEL */
-
-/**
-  * @brief  Helper macro to calculate the PLLPCLK frequency used on ADC domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
-  * @param  __PLLP__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_3
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_5
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_7
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  *         @arg @ref LL_RCC_PLLP_DIV_9
-  *         @arg @ref LL_RCC_PLLP_DIV_10
-  *         @arg @ref LL_RCC_PLLP_DIV_11
-  *         @arg @ref LL_RCC_PLLP_DIV_12
-  *         @arg @ref LL_RCC_PLLP_DIV_13
-  *         @arg @ref LL_RCC_PLLP_DIV_14
-  *         @arg @ref LL_RCC_PLLP_DIV_15
-  *         @arg @ref LL_RCC_PLLP_DIV_16
-  *         @arg @ref LL_RCC_PLLP_DIV_17
-  *         @arg @ref LL_RCC_PLLP_DIV_18
-  *         @arg @ref LL_RCC_PLLP_DIV_19
-  *         @arg @ref LL_RCC_PLLP_DIV_20
-  *         @arg @ref LL_RCC_PLLP_DIV_21
-  *         @arg @ref LL_RCC_PLLP_DIV_22
-  *         @arg @ref LL_RCC_PLLP_DIV_23
-  *         @arg @ref LL_RCC_PLLP_DIV_24
-  *         @arg @ref LL_RCC_PLLP_DIV_25
-  *         @arg @ref LL_RCC_PLLP_DIV_26
-  *         @arg @ref LL_RCC_PLLP_DIV_27
-  *         @arg @ref LL_RCC_PLLP_DIV_28
-  *         @arg @ref LL_RCC_PLLP_DIV_29
-  *         @arg @ref LL_RCC_PLLP_DIV_30
-  *         @arg @ref LL_RCC_PLLP_DIV_31
-  *         @arg @ref LL_RCC_PLLP_DIV_32
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__)  \
-  ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
-   (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
-
-#if defined(RNG)
-/**
-  * @brief  Helper macro to calculate the PLLQCLK frequency used on RNG domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
-  * @param  __PLLQ__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)   \
-  ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /     \
-   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
-#endif /* RNG */
-
-#if defined(RCC_PLLQ_SUPPORT)
-/**
-  * @brief  Helper macro to calculate the PLLQCLK frequency used on TIM1 domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
-  * @param  __PLLQ__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
-  ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /    \
-   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
-#if defined(TIM15)
-/**
-  * @brief  Helper macro to calculate the PLLQCLK frequency used on TIM15 domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM15_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
-  * @param  __PLLQ__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__)  \
-  ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /      \
-   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
-#endif /* TIM15 */
-#endif /* RCC_PLLQ_SUPPORT */
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/**
-  * @brief  Helper macro to calculate the PLLQCLK frequency used on FDCAN domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FDCAN_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
-  * @param  __PLLQ__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
-  ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /     \
-   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
-#endif /* FDCAN1 || FDCAN2 */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Helper macro to calculate the PLLQCLK frequency used on USB domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_USB_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  __PLLN__ Between Min_Data = 8 and Max_Data = 86
-  * @param  __PLLQ__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
-  ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) /   \
-   (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-/**
-  * @brief  Helper macro to calculate the HCLK frequency
-  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
-  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval HCLK clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__)  \
-  ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos] & 0x1FU))
-
-/**
-  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__)  \
-  ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE_Pos] & 0x1FU))
-
-/**
-  * @brief  Helper macro to calculate the HSISYS frequency
-  * @param  __HSIDIV__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_HSI_DIV_1
-  *         @arg @ref LL_RCC_HSI_DIV_2
-  *         @arg @ref LL_RCC_HSI_DIV_4
-  *         @arg @ref LL_RCC_HSI_DIV_8
-  *         @arg @ref LL_RCC_HSI_DIV_16
-  *         @arg @ref LL_RCC_HSI_DIV_32
-  *         @arg @ref LL_RCC_HSI_DIV_64
-  *         @arg @ref LL_RCC_HSI_DIV_128
-  * @retval HSISYS clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos)))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_LL_EF_HSE HSE
-  * @{
-  */
-
-/**
-  * @brief  Enable the Clock Security System.
-  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
-  * @brief  Enable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
-  * @brief  Disable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
-  * @brief  Enable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Disable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Check if HSE oscillator Ready
-  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_HSI HSI
-  * @{
-  */
-
-/**
-  * @brief  Enable HSI even in stop mode
-  * @note HSI oscillator is forced ON even in Stop mode
-  * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSIKERON);
-}
-
-/**
-  * @brief  Disable HSI in stop mode
-  * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
-}
-
-/**
-  * @brief  Check if HSI in stop mode is enabled
-  * @rmtoll CR           HSIKERON        LL_RCC_HSI_IsEnabledInStopMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Disable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Check if HSI clock is ready
-  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get HSI Calibration value
-  * @note When HSITRIM is written, HSICAL is updated with the sum of
-  *       HSITRIM and the factory trim value
-  * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
-  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
-}
-
-/**
-  * @brief  Set HSI Calibration trimming
-  * @note user-programmable trimming value that is added to the HSICAL
-  * @note Default value is 64, which, when added to the HSICAL value,
-  *       should trim the HSI to 16 MHz +/- 1 %
-  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
-  * @param  Value Between Min_Data = 0 and Max_Data = 127
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
-{
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
-}
-
-/**
-  * @brief  Get HSI Calibration trimming
-  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
-  * @retval Between Min_Data = 0 and Max_Data = 127
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
-{
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
-}
-
-/**
-  * @}
-  */
-
-#if defined(RCC_HSI48_SUPPORT)
-/** @defgroup RCC_LL_EF_HSI48 HSI48
-  * @{
-  */
-
-/**
-  * @brief  Enable HSI48
-  * @rmtoll CR         HSI48ON       LL_RCC_HSI48_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSI48ON);
-}
-
-/**
-  * @brief  Disable HSI48
-  * @rmtoll CR          HSI48ON       LL_RCC_HSI48_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
-}
-
-/**
-  * @brief  Check if HSI48 oscillator Ready
-  * @rmtoll CR          HSI48RDY      LL_RCC_HSI48_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get HSI48 Calibration value
-  * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration
-  * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
-}
-
-/**
-  * @}
-  */
-#endif /* RCC_HSI48_SUPPORT */
-
-/** @defgroup RCC_LL_EF_LSE LSE
-  * @{
-  */
-
-/**
-  * @brief  Enable  Low Speed External (LSE) crystal.
-  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
-  * @brief  Disable  Low Speed External (LSE) crystal.
-  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
-  * @brief  Enable external clock source (LSE bypass).
-  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
-  * @brief  Disable external clock source (LSE bypass).
-  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
-  * @brief  Set LSE oscillator drive capability
-  * @note The oscillator is in Xtal mode when it is not in bypass mode.
-  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
-  * @param  LSEDrive This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LSEDRIVE_LOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
-  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
-{
-  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
-}
-
-/**
-  * @brief  Get LSE oscillator drive capability
-  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LSEDRIVE_LOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
-  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
-  *         @arg @ref LL_RCC_LSEDRIVE_HIGH
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
-{
-  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
-}
-
-/**
-  * @brief  Enable Clock security system on LSE.
-  * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
-}
-
-/**
-  * @brief  Disable Clock security system on LSE.
-  * @note Clock security system can be disabled only after a LSE
-  *       failure detection. In that case it MUST be disabled by software.
-  * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_DisableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
-}
-
-/**
-  * @brief  Check if LSE oscillator Ready
-  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
-{
-  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if CSS on LSE failure Detection
-  * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
-{
-  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_LSI LSI
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Disable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Check if LSI is Ready
-  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_LSCO LSCO
-  * @{
-  */
-
-/**
-  * @brief  Enable Low speed clock
-  * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
-}
-
-/**
-  * @brief  Disable Low speed clock
-  * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
-}
-
-/**
-  * @brief  Configure Low speed clock selection
-  * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_SetSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
-}
-
-/**
-  * @brief  Get Low speed clock selection
-  * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_GetSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_System System
-  * @{
-  */
-
-/**
-  * @brief  Configure the system clock source
-  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
-  * @brief  Get the system clock source
-  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
-  * @brief  Set AHB prescaler
-  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
-}
-
-/**
-  * @brief  Set APB1 prescaler
-  * @rmtoll CFGR         PPRE         LL_RCC_SetAPB1Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
-}
-
-/**
-  * @brief  Set HSI16 division factor
-  * @rmtoll CR         HSIDIV          LL_RCC_SetHSIDiv
-  * @note  HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
-  * system clock source.
-  * @param  HSIDiv  This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_HSI_DIV_1
-  *         @arg @ref LL_RCC_HSI_DIV_2
-  *         @arg @ref LL_RCC_HSI_DIV_4
-  *         @arg @ref LL_RCC_HSI_DIV_8
-  *         @arg @ref LL_RCC_HSI_DIV_16
-  *         @arg @ref LL_RCC_HSI_DIV_32
-  *         @arg @ref LL_RCC_HSI_DIV_64
-  *         @arg @ref LL_RCC_HSI_DIV_128
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv)
-{
-  MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv);
-}
-/**
-  * @brief  Get AHB prescaler
-  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
-}
-
-/**
-  * @brief  Get APB1 prescaler
-  * @rmtoll CFGR         PPRE         LL_RCC_GetAPB1Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
-}
-
-/**
-  * @brief  Get HSI16 Division factor
-  * @rmtoll CR         HSIDIV         LL_RCC_GetHSIDiv
-  * @note  HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as
-  * system clock source.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_HSI_DIV_1
-  *         @arg @ref LL_RCC_HSI_DIV_2
-  *         @arg @ref LL_RCC_HSI_DIV_4
-  *         @arg @ref LL_RCC_HSI_DIV_8
-  *         @arg @ref LL_RCC_HSI_DIV_16
-  *         @arg @ref LL_RCC_HSI_DIV_32
-  *         @arg @ref LL_RCC_HSI_DIV_64
-  *         @arg @ref LL_RCC_HSI_DIV_128
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV));
-}
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_MCO1 MCO1
-  * @{
-  */
-
-/**
-  * @brief  Configure MCOx
-  * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
-  *         CFGR         MCOPRE        LL_RCC_ConfigMCO
-  * @param  MCOxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
-  *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
-  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
-  *         @arg @ref LL_RCC_MCO1SOURCE_LSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
-  *         @arg @ref LL_RCC_MCO1SOURCE_PLLPCLK (*)
-  *         @arg @ref LL_RCC_MCO1SOURCE_PLLQCLK (*)
-  *         @arg @ref LL_RCC_MCO1SOURCE_RTCCLK (*)
-  *         @arg @ref LL_RCC_MCO1SOURCE_RTC_WKUP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  MCOxPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1_DIV_1
-  *         @arg @ref LL_RCC_MCO1_DIV_2
-  *         @arg @ref LL_RCC_MCO1_DIV_4
-  *         @arg @ref LL_RCC_MCO1_DIV_8
-  *         @arg @ref LL_RCC_MCO1_DIV_32
-  *         @arg @ref LL_RCC_MCO1_DIV_64
-  *         @arg @ref LL_RCC_MCO1_DIV_128
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
-}
-
-/**
-  * @}
-  */
-
-#if defined(RCC_MCO2_SUPPORT)
-/** @defgroup RCC_LL_EF_MCO2 MCO2
-  * @{
-  */
-
-/**
-  * @brief  Configure MCO2
-  * @rmtoll CFGR         MCO2SEL        LL_RCC_ConfigMCO2\n
-  *         CFGR         MCO2PRE        LL_RCC_ConfigMCO2
-  * @note  feature not available in all devices.
-  * @param  MCOxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK
-  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_HSI
-  *         @arg @ref LL_RCC_MCO2SOURCE_HSI48
-  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
-  *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_LSI
-  *         @arg @ref LL_RCC_MCO2SOURCE_LSE
-  *         @arg @ref LL_RCC_MCO2SOURCE_PLLPCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_PLLQCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_RTCCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_RTC_WKUP
-  *
-  * @param  MCOxPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO2_DIV_1
-  *         @arg @ref LL_RCC_MCO2_DIV_2
-  *         @arg @ref LL_RCC_MCO2_DIV_4
-  *         @arg @ref LL_RCC_MCO2_DIV_8
-  *         @arg @ref LL_RCC_MCO2_DIV_16
-  *         @arg @ref LL_RCC_MCO2_DIV_32
-  *         @arg @ref LL_RCC_MCO2_DIV_64
-  *         @arg @ref LL_RCC_MCO2_DIV_128
-  *         @arg @ref LL_RCC_MCO2_DIV_256
-  *         @arg @ref LL_RCC_MCO2_DIV_512
-  *         @arg @ref LL_RCC_MCO2_DIV_1024
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE, MCOxSource | MCOxPrescaler);
-}
-
-/**
-  * @}
-  */
-#endif /* RCC_MCO2_SUPPORT */
-
-/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
-  * @{
-  */
-
-/**
-  * @brief  Configure USARTx clock source
-  * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource
-  * @param  USARTxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
-{
-  MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
-}
-
-#if defined(LPUART1)
-/**
-  * @brief  Configure LPUARTx clock source
-  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
-  * @rmtoll CCIPR        LPUART2SEL    LL_RCC_SetLPUARTClockSource
-  * @param  LPUARTxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*)
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*)
-  * (*) feature not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
-{
-  MODIFY_REG(RCC->CCIPR, (LPUARTxSource >> 16U), (LPUARTxSource & 0x0000FFFFU));
-}
-#endif /* LPUART1 */
-
-/**
-  * @brief  Configure I2Cx clock source
-  * @rmtoll CCIPR        I2C1SEL       LL_RCC_SetI2CClockSource
-  * @param  I2CxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
-  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
-  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
-{
-  MODIFY_REG(RCC->CCIPR, (I2CxSource >> 16U), (I2CxSource & 0x0000FFFFU));
-}
-
-#if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
-/**
-  * @brief  Configure TIMx clock source
-  * @rmtoll CCIPR        TIMxSEL       LL_RCC_SetTIMClockSource
-  * @param  TIMxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
-  * @if defined(STM32G081xx)
-  *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
-  * @endif
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
-{
-  MODIFY_REG(RCC->CCIPR, (TIMxSource & 0xFFFF0000U), (TIMxSource << 16));
-}
-#endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */
-
-#if defined(LPTIM1) && defined(LPTIM2)
-/**
-  * @brief  Configure LPTIMx clock source
-  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_SetLPTIMClockSource
-  * @param  LPTIMxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
-{
-  MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
-}
-#endif /* LPTIM1 && LPTIM2 */
-
-#if defined(CEC)
-/**
-  * @brief  Configure CEC clock source
-  * @rmtoll CCIPR        CECSEL        LL_RCC_SetCECClockSource
-  * @param  CECxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
-{
-  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, CECxSource);
-}
-#endif /* CEC */
-
-#if defined(RCC_CCIPR_RNGDIV)
-/**
-  * @brief  Configure RNG division factor
-  * @rmtoll CCIPR        RNGDIV        LL_RCC_SetRNGClockDiv
-  * @param  RNGxDiv This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLK_DIV1
-  *         @arg @ref LL_RCC_RNG_CLK_DIV2
-  *         @arg @ref LL_RCC_RNG_CLK_DIV4
-  *         @arg @ref LL_RCC_RNG_CLK_DIV8
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRNGClockDiv(uint32_t RNGxDiv)
-{
-  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, RNGxDiv);
-}
-#endif /* RNG */
-
-#if defined (RCC_CCIPR_RNGSEL)
-/**
-  * @brief  Configure RNG clock source
-  * @rmtoll CCIPR        RNGSEL        LL_RCC_SetRNGClockSource
-  * @param  RNGxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
-{
-  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
-}
-#endif /* RNG */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Configure USB clock source
-  * @rmtoll CCIPR2        CK48MSEL      LL_RCC_SetUSBClockSource
-  * @param  USBxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
-{
-  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, USBxSource);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-#if defined (FDCAN1) || defined (FDCAN2)
-/**
-  * @brief  Configure FDCAN clock source
-  * @rmtoll CCIPR2        FDCANSEL        LL_RCC_SetFDCANClockSource
-  * @param  FDCANxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
-{
-  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, FDCANxSource);
-}
-#endif /* FDCAN1 || FDCAN2 */
-
-/**
-  * @brief  Configure ADC clock source
-  * @rmtoll CCIPR        ADCSEL        LL_RCC_SetADCClockSource
-  * @param  ADCxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
-{
-  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Configure I2Sx clock source
-  * @rmtoll CCIPR2        I2SxSEL       LL_RCC_SetI2SClockSource
-  * @param  I2SxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
-{
-  MODIFY_REG(RCC->CCIPR2, (I2SxSource >> 16U), (I2SxSource & 0x0000FFFFU));
-}
-
-#else
-/**
-  * @brief  Configure I2Sx clock source
-  * @rmtoll CCIPR        I2S1SEL       LL_RCC_SetI2SClockSource
-  * @param  I2SxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
-{
-  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, I2SxSource);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-/**
-  * @brief  Get USARTx clock source
-  * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource
-  * @param  USARTx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
-  * (*) feature not available on all devices
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
-}
-
-#if defined (LPUART2) || defined (LPUART1)
-/**
-  * @brief  Get LPUARTx clock source
-  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource\n
-  *         CCIPR        LPUART2SEL    LL_RCC_GetLPUARTClockSource
-  * @param  LPUARTx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE (*)
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*)
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*)
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*)
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*)
-  * (*) feature not available on all devices
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx) | (LPUARTx << 16U));
-}
-#endif /* LPUART2 || LPUART1 */
-
-/**
-  * @brief  Get I2Cx clock source
-  * @rmtoll CCIPR        I2C1SEL       LL_RCC_GetI2CClockSource\n
-  *         CCIPR        I2C2SEL       LL_RCC_GetI2CClockSource
-  * @param  I2Cx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
-  *         @arg @ref LL_RCC_I2C2_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, I2Cx) | (I2Cx << 16U));
-}
-
-#if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
-/**
-  * @brief  Get TIMx clock source
-  * @rmtoll CCIPR        TIMxSEL       LL_RCC_GetTIMClockSource
-  * @param  TIMx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_TIM1_CLKSOURCE
-  *         @arg @ref LL_RCC_TIM15_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1
-  * @if defined(STM32G081xx)
-  *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1
-  * @endif
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
-{
-  return (uint32_t)((READ_BIT(RCC->CCIPR, TIMx) >> 16U) | TIMx);
-}
-#endif /* RCC_CCIPR_TIM1SEL || RCC_CCIPR_TIM15SEL */
-
-#if defined(LPTIM1) && defined(LPTIM2)
-/**
-  * @brief  Get LPTIMx clock source
-  * @rmtoll CCIPR        LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n
-            CCIPR        LPTIM2SEL     LL_RCC_GetLPTIMClockSource
-  * @param  LPTIMx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
-{
-  return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx);
-}
-#endif /* LPTIM1 && LPTIM2 */
-
-#if defined (RCC_CCIPR_CECSEL)
-/**
-  * @brief  Get CEC clock source
-  * @rmtoll CCIPR        CECSEL        LL_RCC_GetCECClockSource
-  * @param  CECx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, CECx));
-}
-#endif /* CEC */
-
-#if defined(RCC_CCIPR2_FDCANSEL)
-/**
-  * @brief  Get FDCAN clock source
-  * @rmtoll CCIPR2        FDCANSEL        LL_RCC_GetFDCANClockSource
-  * @param  FDCANx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR2, FDCANx));
-}
-#endif /* RCC_CCIPR2_FDCANSEL */
-
-#if defined(RNG)
-/**
-  * @brief  Get RNGx clock source
-  * @rmtoll CCIPR        RNGSEL        LL_RCC_GetRNGClockSource
-  * @param  RNGx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
-}
-#endif /* RNG */
-
-#if defined(RNG)
-/**
-  * @brief  Get RNGx clock division factor
-  * @rmtoll CCIPR        RNGDIV        LL_RCC_GetRNGClockDiv
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLK_DIV1
-  *         @arg @ref LL_RCC_RNG_CLK_DIV2
-  *         @arg @ref LL_RCC_RNG_CLK_DIV4
-  *         @arg @ref LL_RCC_RNG_CLK_DIV8
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRNGClockDiv(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV));
-}
-#endif /* RNG */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Get USBx clock source
-  * @rmtoll CCIPR2        CK48MSEL        LL_RCC_GetUSBClockSource
-  * @param  USBx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR2, USBx));
-}
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-/**
-  * @brief  Get ADCx clock source
-  * @rmtoll CCIPR        ADCSEL        LL_RCC_GetADCClockSource
-  * @param  ADCx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Get I2Sx clock source
-  * @rmtoll CCIPR2        I2S1SEL     LL_RCC_GetI2SClockSource\n
-  *         CCIPR2        I2S2SEL     LL_RCC_GetI2SClockSource
-  * @param  I2Sx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR2, I2Sx) | (I2Sx << 16U));
-}
-#else
-/**
-  * @brief  Get I2Sx clock source
-  * @rmtoll CCIPR        I2S1SEL        LL_RCC_GetI2SClockSource
-  * @param  I2Sx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
-{
-  return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
-}
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_RTC RTC
-  * @{
-  */
-
-/**
-  * @brief  Set RTC Clock Source
-  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
-  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
-  *       set). The BDRST bit can be used to reset them.
-  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
-}
-
-/**
-  * @brief  Get RTC Clock Source
-  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
-}
-
-/**
-  * @brief  Enable RTC
-  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableRTC(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
-  * @brief  Disable RTC
-  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableRTC(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
-  * @brief  Check if RTC has been enabled or not
-  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
-{
-  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Force the Backup domain reset
-  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
-  * @brief  Release the Backup domain reset
-  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_LL_EF_PLL PLL
-  * @{
-  */
-
-/**
-  * @brief  Enable PLL
-  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
-  * @brief  Disable PLL
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
-  * @brief  Check if PLL Ready
-  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
-{
-  return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure PLL used for SYSCLK Domain
-  * @note PLL Source and PLLM Divider can be written only when PLL is disabled
-  * @note PLLN/PLLR can be written only when PLL is disabled
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
-  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  PLLN Between 8 and 86
-  * @param  PLLR This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  *         @arg @ref LL_RCC_PLLR_DIV_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
-             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
-}
-
-/**
-  * @brief  Configure PLL used for ADC domain clock
-  * @note   PLL Source and PLLM Divider can be written only when PLL is disabled
-  * @note   PLLN/PLLP can be written only when PLL is disabled
-  * @note   User shall verify whether the PLL configuration is not done through
-  *         other functions (ex: I2S1)
-  * @note   This can be selected for ADC
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_ADC\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_ADC\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_ADC\n
-  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_ADC
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  PLLN Between 8 and 86
-  * @param  PLLP This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_3
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_5
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_7
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  *         @arg @ref LL_RCC_PLLP_DIV_9
-  *         @arg @ref LL_RCC_PLLP_DIV_10
-  *         @arg @ref LL_RCC_PLLP_DIV_11
-  *         @arg @ref LL_RCC_PLLP_DIV_12
-  *         @arg @ref LL_RCC_PLLP_DIV_13
-  *         @arg @ref LL_RCC_PLLP_DIV_14
-  *         @arg @ref LL_RCC_PLLP_DIV_15
-  *         @arg @ref LL_RCC_PLLP_DIV_16
-  *         @arg @ref LL_RCC_PLLP_DIV_17
-  *         @arg @ref LL_RCC_PLLP_DIV_18
-  *         @arg @ref LL_RCC_PLLP_DIV_19
-  *         @arg @ref LL_RCC_PLLP_DIV_20
-  *         @arg @ref LL_RCC_PLLP_DIV_21
-  *         @arg @ref LL_RCC_PLLP_DIV_22
-  *         @arg @ref LL_RCC_PLLP_DIV_23
-  *         @arg @ref LL_RCC_PLLP_DIV_24
-  *         @arg @ref LL_RCC_PLLP_DIV_25
-  *         @arg @ref LL_RCC_PLLP_DIV_26
-  *         @arg @ref LL_RCC_PLLP_DIV_27
-  *         @arg @ref LL_RCC_PLLP_DIV_28
-  *         @arg @ref LL_RCC_PLLP_DIV_29
-  *         @arg @ref LL_RCC_PLLP_DIV_30
-  *         @arg @ref LL_RCC_PLLP_DIV_31
-  *         @arg @ref LL_RCC_PLLP_DIV_32
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
-             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
-}
-
-/**
-  * @brief  Configure PLL used for I2S1 domain clock
-  * @note   PLL Source and PLLM Divider can be written only when PLL is disabled
-  * @note   PLLN/PLLP can be written only when PLL is disabled
-  * @note   User shall verify whether the PLL configuration is not done through
-  *         other functions (ex: ADC)
-  * @note   This can be selected for I2S1
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_I2S1\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_I2S1\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_I2S1\n
-  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_I2S1
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  PLLN Between 8 and 86
-  * @param  PLLP This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_3
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_5
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_7
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  *         @arg @ref LL_RCC_PLLP_DIV_9
-  *         @arg @ref LL_RCC_PLLP_DIV_10
-  *         @arg @ref LL_RCC_PLLP_DIV_11
-  *         @arg @ref LL_RCC_PLLP_DIV_12
-  *         @arg @ref LL_RCC_PLLP_DIV_13
-  *         @arg @ref LL_RCC_PLLP_DIV_14
-  *         @arg @ref LL_RCC_PLLP_DIV_15
-  *         @arg @ref LL_RCC_PLLP_DIV_16
-  *         @arg @ref LL_RCC_PLLP_DIV_17
-  *         @arg @ref LL_RCC_PLLP_DIV_18
-  *         @arg @ref LL_RCC_PLLP_DIV_19
-  *         @arg @ref LL_RCC_PLLP_DIV_20
-  *         @arg @ref LL_RCC_PLLP_DIV_21
-  *         @arg @ref LL_RCC_PLLP_DIV_22
-  *         @arg @ref LL_RCC_PLLP_DIV_23
-  *         @arg @ref LL_RCC_PLLP_DIV_24
-  *         @arg @ref LL_RCC_PLLP_DIV_25
-  *         @arg @ref LL_RCC_PLLP_DIV_26
-  *         @arg @ref LL_RCC_PLLP_DIV_27
-  *         @arg @ref LL_RCC_PLLP_DIV_28
-  *         @arg @ref LL_RCC_PLLP_DIV_29
-  *         @arg @ref LL_RCC_PLLP_DIV_30
-  *         @arg @ref LL_RCC_PLLP_DIV_31
-  *         @arg @ref LL_RCC_PLLP_DIV_32
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
-             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
-}
-
-#if defined(RCC_CCIPR2_I2S2SEL)
-/**
-  * @brief  Configure PLL used for I2S2 domain clock
-  * @note   PLL Source and PLLM Divider can be written only when PLL is disabled
-  * @note   PLLN/PLLP can be written only when PLL is disabled
-  * @note   User shall verify whether the PLL configuration is not done through
-  *         other functions (ex: ADC)
-  * @note   This can be selected for I2S2
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_I2S2\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_I2S2\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_I2S2\n
-  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_I2S2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  PLLN Between 8 and 86
-  * @param  PLLP This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_3
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_5
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_7
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  *         @arg @ref LL_RCC_PLLP_DIV_9
-  *         @arg @ref LL_RCC_PLLP_DIV_10
-  *         @arg @ref LL_RCC_PLLP_DIV_11
-  *         @arg @ref LL_RCC_PLLP_DIV_12
-  *         @arg @ref LL_RCC_PLLP_DIV_13
-  *         @arg @ref LL_RCC_PLLP_DIV_14
-  *         @arg @ref LL_RCC_PLLP_DIV_15
-  *         @arg @ref LL_RCC_PLLP_DIV_16
-  *         @arg @ref LL_RCC_PLLP_DIV_17
-  *         @arg @ref LL_RCC_PLLP_DIV_18
-  *         @arg @ref LL_RCC_PLLP_DIV_19
-  *         @arg @ref LL_RCC_PLLP_DIV_20
-  *         @arg @ref LL_RCC_PLLP_DIV_21
-  *         @arg @ref LL_RCC_PLLP_DIV_22
-  *         @arg @ref LL_RCC_PLLP_DIV_23
-  *         @arg @ref LL_RCC_PLLP_DIV_24
-  *         @arg @ref LL_RCC_PLLP_DIV_25
-  *         @arg @ref LL_RCC_PLLP_DIV_26
-  *         @arg @ref LL_RCC_PLLP_DIV_27
-  *         @arg @ref LL_RCC_PLLP_DIV_28
-  *         @arg @ref LL_RCC_PLLP_DIV_29
-  *         @arg @ref LL_RCC_PLLP_DIV_30
-  *         @arg @ref LL_RCC_PLLP_DIV_31
-  *         @arg @ref LL_RCC_PLLP_DIV_32
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S2(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
-             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
-}
-#endif /* RCC_CCIPR2_I2S2SEL */
-
-#if defined(RNG)
-/**
-  * @brief  Configure PLL used for RNG domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL is disabled
-  * @note PLLN/PLLQ can be written only when PLL is disabled
-  * @note   User shall verify whether the PLL configuration is not done through
-  *         other functions (ex: TIM1, TIM15)
-  * @note This  can be selected for RNG
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_RNG\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_RNG\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_RNG\n
-  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_RNG
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  PLLN Between 8 and 86
-  * @param  PLLQ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
-             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
-}
-#endif /* RNG */
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/**
-  * @brief  Configure PLL used for FDCAN domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL is disabled
-  * @note PLLN/PLLQ can be written only when PLL is disabled
-  * @note   User shall verify whether the PLL configuration is not done through
-  *         other functions (ex: TIM1, TIM15)
-  * @note This  can be selected for FDCAN
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_FDCAN\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_FDCAN\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_FDCAN\n
-  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_FDCAN
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  PLLN Between 8 and 86
-  * @param  PLLQ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_FDCAN(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
-             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
-}
-#endif /* FDCAN1 || FDCAN2 */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Configure PLL used for USB domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL is disabled
-  * @note PLLN/PLLQ can be written only when PLL is disabled
-  * @note   User shall verify whether the PLL configuration is not done through
-  *         other functions (ex: TIM1, TIM15)
-  * @note This  can be selected for USB
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_USB\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_USB\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_USB\n
-  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_USB
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  PLLN Between 8 and 86
-  * @param  PLLQ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_USB(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
-             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-#if defined(RCC_PLLQ_SUPPORT)
-/**
-  * @brief  Configure PLL used for TIM1 domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL is disabled
-  * @note PLLN/PLLQ can be written only when PLL is disabled
-  * @note   User shall verify whether the PLL configuration is not done through
-  *         other functions (ex: RNG, TIM15)
-  * @note This  can be selected for TIM1
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_TIM1\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_TIM1\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_TIM1\n
-  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_TIM1
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  PLLN Between 8 and 86
-  * @param  PLLQ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
-             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
-}
-#endif /* RCC_PLLQ_SUPPORT */
-
-#if defined(RCC_PLLQ_SUPPORT) && defined(TIM15)
-/**
-  * @brief  Configure PLL used for TIM15 domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL is disabled
-  * @note PLLN/PLLQ can be written only when PLL is disabled
-  * @note   User shall verify whether the PLL configuration is not done through
-  *         other functions (ex: RNG, TIM1)
-  * @note This  can be selected for TIM15
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_TIM15\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_TIM15\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_TIM15\n
-  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_TIM15
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  * @param  PLLN Between 8 and 86
-  * @param  PLLQ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM15(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
-             Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
-}
-#endif /* RCC_PLLQ_SUPPORT && TIM15 */
-
-/**
-  * @brief  Get Main PLL multiplication factor for VCO
-  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
-  * @retval Between 8 and 86
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
-}
-
-/**
-  * @brief  Get Main PLL division factor for PLLP
-  * @note   used for PLLPCLK (ADC & I2S clock)
-  * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_3
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_5
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_7
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  *         @arg @ref LL_RCC_PLLP_DIV_9
-  *         @arg @ref LL_RCC_PLLP_DIV_10
-  *         @arg @ref LL_RCC_PLLP_DIV_11
-  *         @arg @ref LL_RCC_PLLP_DIV_12
-  *         @arg @ref LL_RCC_PLLP_DIV_13
-  *         @arg @ref LL_RCC_PLLP_DIV_14
-  *         @arg @ref LL_RCC_PLLP_DIV_15
-  *         @arg @ref LL_RCC_PLLP_DIV_16
-  *         @arg @ref LL_RCC_PLLP_DIV_17
-  *         @arg @ref LL_RCC_PLLP_DIV_18
-  *         @arg @ref LL_RCC_PLLP_DIV_19
-  *         @arg @ref LL_RCC_PLLP_DIV_20
-  *         @arg @ref LL_RCC_PLLP_DIV_21
-  *         @arg @ref LL_RCC_PLLP_DIV_22
-  *         @arg @ref LL_RCC_PLLP_DIV_23
-  *         @arg @ref LL_RCC_PLLP_DIV_24
-  *         @arg @ref LL_RCC_PLLP_DIV_25
-  *         @arg @ref LL_RCC_PLLP_DIV_26
-  *         @arg @ref LL_RCC_PLLP_DIV_27
-  *         @arg @ref LL_RCC_PLLP_DIV_28
-  *         @arg @ref LL_RCC_PLLP_DIV_29
-  *         @arg @ref LL_RCC_PLLP_DIV_30
-  *         @arg @ref LL_RCC_PLLP_DIV_31
-  *         @arg @ref LL_RCC_PLLP_DIV_32
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
-}
-
-#if defined(RCC_PLLQ_SUPPORT)
-/**
-  * @brief  Get Main PLL division factor for PLLQ
-  * @note used for PLLQCLK selected for RNG, TIM1, TIM15 clock
-  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
-}
-#endif /* RCC_PLLQ_SUPPORT */
-
-/**
-  * @brief  Get Main PLL division factor for PLLR
-  * @note used for PLLCLK (system clock)
-  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  *         @arg @ref LL_RCC_PLLR_DIV_8
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
-}
-
-/**
-  * @brief  Configure PLL clock source
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
-  * @param PLLSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
-}
-
-/**
-  * @brief  Get the oscillator used as PLL clock source.
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_NONE
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
-}
-
-/**
-  * @brief  Get Division factor for the main PLL and other PLL
-  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_1
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
-}
-
-/**
-  * @brief  Enable PLL output mapped on ADC domain clock
-  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_ADC
-  * @note   User shall check that PLL enable is not done through
-  *         other functions (ex: I2S1)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
-}
-
-/**
-  * @brief  Disable PLL output mapped on ADC domain clock
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @note   User shall check that PLL is not used by any other peripheral
-  *         (ex: I2S1)
-  * @note In order to save power, when the PLLCLK  of the PLL is
-  *       not used,  should be 0
-  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_ADC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
-}
-
-/**
-  * @brief  Enable PLL output mapped on I2S domain clock
-  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_I2S1
-  * @note   User shall check that PLL enable is not done through
-  *         other functions (ex: ADC)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S1(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
-}
-
-#if defined(RCC_CCIPR2_I2S2SEL)
-/**
-  * @brief  Enable PLL output mapped on I2S2 domain clock
-  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_I2S2
-  * @note   User shall check that PLL enable is not done through
-  *         other functions (ex: ADC)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S2(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
-}
-#endif /* RCC_CCIPR2_I2S2SEL */
-
-/**
-  * @brief  Disable PLL output mapped on I2S1 domain clock
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @note   User shall check that PLL is not used by any other peripheral
-  *         (ex: RNG)
-  * @note In order to save power, when the PLLCLK  of the PLL is
-  *       not used,  should be 0
-  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_I2S1
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S1(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
-}
-
-#if defined(RCC_CCIPR2_I2S2SEL)
-/**
-  * @brief  Disable PLL output mapped on I2S2 domain clock
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @note   User shall check that PLL is not used by any other peripheral
-  *         (ex: RNG)
-  * @note In order to save power, when the PLLCLK  of the PLL is
-  *       not used,  should be 0
-  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_I2S2
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S2(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
-}
-#endif /* RCC_CCIPR2_I2S2SEL */
-
-#if defined(RNG)
-/**
-  * @brief  Enable PLL output mapped on RNG domain clock
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_RNG
-  * @note   User shall check that PLL enable is not done through
-  *         other functions (ex: TIM1, TIM15)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-
-/**
-  * @brief  Disable PLL output mapped on RNG domain clock
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @note   User shall check that PLL is not used by any other peripheral
-  *         (ex: TIM, TIM15)
-  * @note In order to save power, when the PLLCLK  of the PLL is
-  *       not used,  should be 0
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_RNG
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-#endif /* RNG */
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/**
-  * @brief  Enable PLL output mapped on FDCAN domain clock
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_FDCAN
-  * @note   User shall check that PLL enable is not done through
-  *         other functions (ex: TIM1, TIM15)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_FDCAN(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-
-/**
-  * @brief  Disable PLL output mapped on FDCAN domain clock
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @note   User shall check that PLL is not used by any other peripheral
-  *         (ex: TIM, TIM15)
-  * @note In order to save power, when the PLLCLK  of the PLL is
-  *       not used,  should be 0
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_FDCAN
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_FDCAN(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-#endif /* FDCAN1 || FDCAN2 */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Enable PLL output mapped on USB domain clock
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_USB
-  * @note   User shall check that PLL enable is not done through
-  *         other functions (ex: TIM1, TIM15)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_USB(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-
-/**
-  * @brief  Disable PLL output mapped on USB domain clock
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @note   User shall check that PLL is not used by any other peripheral
-  *         (ex: TIM, TIM15)
-  * @note In order to save power, when the PLLCLK  of the PLL is
-  *       not used,  should be 0
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_USB
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_USB(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-#if defined(RCC_PLLQ_SUPPORT)
-/**
-  * @brief  Enable PLL output mapped on TIM1 domain clock
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_TIM1
-  * @note   User shall check that PLL enable is not done through
-  *         other functions (ex: RNG, TIM15)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM1(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-
-/**
-  * @brief  Disable PLL output mapped on TIM1 domain clock
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @note   User shall check that PLL is not used by any other peripheral
-  *         (ex: RNG, TIM15)
-  * @note In order to save power, when the PLLCLK  of the PLL is
-  *       not used,  should be 0
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_TIM1
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM1(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-#endif /* RCC_PLLQ_SUPPORT */
-
-#if defined(RCC_PLLQ_SUPPORT) && defined(TIM15)
-/**
-  * @brief  Enable PLL output mapped on TIM15 domain clock
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_TIM15
-  * @note   User shall check that PLL enable is not done through
-  *         other functions (ex: RNG, TIM1)
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM15(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-
-/**
-  * @brief  Disable PLL output mapped on TIM15 domain clock
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @note   User shall check that PLL is not used by any other peripheral
-  *         (ex: RNG, TIM1)
-  * @note In order to save power, when the PLLCLK  of the PLL is
-  *       not used,  should be 0
-  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_TIM15
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM15(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
-}
-#endif /* RCC_PLLQ_SUPPORT && TIM15 */
-
-/**
-  * @brief  Enable PLL output mapped on SYSCLK domain
-  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
-{
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
-}
-
-/**
-  * @brief  Disable PLL output mapped on SYSCLK domain
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @note In order to save power, when the PLLCLK  of the PLL is
-  *       not used, Main PLL  should be 0
-  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_DisableDomain_SYS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
-{
-  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
-}
-
-/**
-  * @}
-  */
-
-
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Clear LSI ready interrupt flag
-  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
-}
-
-/**
-  * @brief  Clear LSE ready interrupt flag
-  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
-}
-
-/**
-  * @brief  Clear HSI ready interrupt flag
-  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
-}
-
-/**
-  * @brief  Clear HSE ready interrupt flag
-  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
-}
-
-/**
-  * @brief  Clear PLL ready interrupt flag
-  * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Clear HSI48 ready interrupt flag
-  * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
-}
-#endif /* RCC_HSI48_SUPPORT */
-/**
-  * @brief  Clear Clock security system interrupt flag
-  * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_CSSC);
-}
-
-/**
-  * @brief  Clear LSE Clock security system interrupt flag
-  * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
-{
-  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
-}
-
-/**
-  * @brief  Check if LSI ready interrupt occurred or not
-  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if LSE ready interrupt occurred or not
-  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if HSI ready interrupt occurred or not
-  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if HSE ready interrupt occurred or not
-  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if PLL ready interrupt occurred or not
-  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Check if HSI48 ready interrupt occurred or not
-  * @rmtoll CIR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
-}
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
-  * @brief  Check if Clock security system interrupt occurred or not
-  * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if LSE Clock security system interrupt occurred or not
-  * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
-{
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
-  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Low Power reset is set or not.
-  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Option byte reset is set or not.
-  * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Pin reset is set or not.
-  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Software reset is set or not.
-  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag Window Watchdog reset is set or not.
-  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if RCC flag BOR or POR/PDR reset is set or not.
-  * @rmtoll CSR          PWRRSTF       LL_RCC_IsActiveFlag_PWRRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void)
-{
-  return ((READ_BIT(RCC->CSR, RCC_CSR_PWRRSTF) == (RCC_CSR_PWRRSTF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set RMVF bit to clear the reset flags.
-  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI ready interrupt
-  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
-}
-
-/**
-  * @brief  Enable LSE ready interrupt
-  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
-}
-
-/**
-  * @brief  Enable HSI ready interrupt
-  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
-}
-
-/**
-  * @brief  Enable HSE ready interrupt
-  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
-}
-
-/**
-  * @brief  Enable PLL ready interrupt
-  * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Enable HSI48 ready interrupt
-  * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
-{
-  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
-}
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
-  * @brief  Disable LSI ready interrupt
-  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
-}
-
-/**
-  * @brief  Disable LSE ready interrupt
-  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
-}
-
-/**
-  * @brief  Disable HSI ready interrupt
-  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
-}
-
-/**
-  * @brief  Disable HSE ready interrupt
-  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
-}
-
-/**
-  * @brief  Disable PLL ready interrupt
-  * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Disable HSI48 ready interrupt
-  * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
-{
-  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
-}
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
-  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
-}
-
-#if defined(RCC_HSI48_SUPPORT)
-/**
-  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         HSI48RDYIE      LL_RCC_IsEnabledIT_HSI48RDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
-}
-#endif /* RCC_HSI48_SUPPORT */
-
-/**
-  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
-  * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
-{
-  return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
-  * @{
-  */
-ErrorStatus LL_RCC_DeInit(void);
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
-  * @{
-  */
-void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
-uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
-#if defined(LPUART1) || defined(LPUART2)
-uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
-#endif /* LPUART1 */
-#if defined(LPTIM1) && defined(LPTIM2)
-uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
-#endif /* LPTIM1 && LPTIM2 */
-#if defined(RNG)
-uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
-#endif /* RNG */
-uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
-uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
-#if defined(CEC)
-uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
-#endif /* CEC */
-#if defined(FDCAN1) || defined(FDCAN2)
-uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
-#endif /* FDCAN1 */
-uint32_t    LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
-uint32_t    LL_RCC_GetRTCClockFreq(void);
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* RCC */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_spi.h

@@ -1,2286 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_spi.h
-  * @author  MCD Application Team
-  * @brief   Header file of SPI LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_SPI_H
-#define STM32G0xx_LL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3)
-
-/** @defgroup SPI_LL SPI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  SPI Init structures definition
-  */
-typedef struct
-{
-  uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
-                                         This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
-
-  uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
-                                         This parameter can be a value of @ref SPI_LL_EC_MODE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
-
-  uint32_t DataWidth;               /*!< Specifies the SPI data width.
-                                         This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
-
-  uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
-                                         This parameter can be a value of @ref SPI_LL_EC_POLARITY.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
-
-  uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
-                                         This parameter can be a value of @ref SPI_LL_EC_PHASE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
-
-  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
-                                         This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
-
-  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
-                                         This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
-                                         @note The communication clock is derived from the master clock. The slave clock does not need to be set.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
-
-  uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                         This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
-
-  uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
-                                         This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
-
-                                         This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
-
-  uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
-                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
-
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
-
-} LL_SPI_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_SPI_ReadReg function
-  * @{
-  */
-#define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
-#define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
-#define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
-#define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
-#define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
-#define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
-#define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
-  * @{
-  */
-#define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
-#define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
-#define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_MODE Operation Mode
-  * @{
-  */
-#define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
-#define LL_SPI_MODE_SLAVE                  0x00000000U                     /*!< Slave configuration   */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
-  * @{
-  */
-#define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
-#define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_PHASE Clock Phase
-  * @{
-  */
-#define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
-#define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
-#define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
-  * @{
-  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
-#define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
-  * @{
-  */
-#define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
-  * @{
-  */
-#define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
-#define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
-#define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
-#define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
-  * @{
-  */
-#define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
-#define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
-#define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_SPI_DATAWIDTH_4BIT              (SPI_CR2_DS_0 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  4 bits */
-#define LL_SPI_DATAWIDTH_5BIT              (SPI_CR2_DS_2)                                              /*!< Data length for SPI transfer:  5 bits */
-#define LL_SPI_DATAWIDTH_6BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer:  6 bits */
-#define LL_SPI_DATAWIDTH_7BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer:  7 bits */
-#define LL_SPI_DATAWIDTH_8BIT              (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer:  8 bits */
-#define LL_SPI_DATAWIDTH_9BIT              (SPI_CR2_DS_3)                                              /*!< Data length for SPI transfer:  9 bits */
-#define LL_SPI_DATAWIDTH_10BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_0)                               /*!< Data length for SPI transfer: 10 bits */
-#define LL_SPI_DATAWIDTH_11BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1)                               /*!< Data length for SPI transfer: 11 bits */
-#define LL_SPI_DATAWIDTH_12BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 12 bits */
-#define LL_SPI_DATAWIDTH_13BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2)                               /*!< Data length for SPI transfer: 13 bits */
-#define LL_SPI_DATAWIDTH_14BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0)                /*!< Data length for SPI transfer: 14 bits */
-#define LL_SPI_DATAWIDTH_15BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1)                /*!< Data length for SPI transfer: 15 bits */
-#define LL_SPI_DATAWIDTH_16BIT             (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
-  * @{
-  */
-#define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U               /*!< CRC calculation disabled */
-#define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)           /*!< CRC calculation enabled  */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
-  * @{
-  */
-#define LL_SPI_CRC_8BIT                    0x00000000U               /*!<  8-bit CRC length */
-#define LL_SPI_CRC_16BIT                   (SPI_CR1_CRCL)            /*!< 16-bit CRC length */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
-  * @{
-  */
-#define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
-#define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit)  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
-  * @{
-  */
-#define LL_SPI_RX_FIFO_EMPTY               0x00000000U                       /*!< FIFO reception empty */
-#define LL_SPI_RX_FIFO_QUARTER_FULL        (SPI_SR_FRLVL_0)                  /*!< FIFO reception 1/4   */
-#define LL_SPI_RX_FIFO_HALF_FULL           (SPI_SR_FRLVL_1)                  /*!< FIFO reception 1/2   */
-#define LL_SPI_RX_FIFO_FULL                (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
-  * @{
-  */
-#define LL_SPI_TX_FIFO_EMPTY               0x00000000U                       /*!< FIFO transmission empty */
-#define LL_SPI_TX_FIFO_QUARTER_FULL        (SPI_SR_FTLVL_0)                  /*!< FIFO transmission 1/4   */
-#define LL_SPI_TX_FIFO_HALF_FULL           (SPI_SR_FTLVL_1)                  /*!< FIFO transmission 1/2   */
-#define LL_SPI_TX_FIFO_FULL                (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
-  * @{
-  */
-#define LL_SPI_DMA_PARITY_EVEN             0x00000000U   /*!< Select DMA parity Even */
-#define LL_SPI_DMA_PARITY_ODD              0x00000001U   /*!< Select DMA parity Odd  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in SPI register
-  * @param  __INSTANCE__ SPI Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in SPI register
-  * @param  __INSTANCE__ SPI Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
-  * @{
-  */
-
-/** @defgroup SPI_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Enable SPI peripheral
-  * @rmtoll CR1          SPE           LL_SPI_Enable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
-  * @brief  Disable SPI peripheral
-  * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
-  * @rmtoll CR1          SPE           LL_SPI_Disable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
-  * @brief  Check if SPI peripheral is enabled
-  * @rmtoll CR1          SPE           LL_SPI_IsEnabled
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set SPI operation mode to Master or Slave
-  * @note   This bit should not be changed when communication is ongoing.
-  * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
-  *         CR1          SSI           LL_SPI_SetMode
-  * @param  SPIx SPI Instance
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_MODE_MASTER
-  *         @arg @ref LL_SPI_MODE_SLAVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
-}
-
-/**
-  * @brief  Get SPI operation mode (Master or Slave)
-  * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
-  *         CR1          SSI           LL_SPI_GetMode
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_MODE_MASTER
-  *         @arg @ref LL_SPI_MODE_SLAVE
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
-}
-
-/**
-  * @brief  Set serial protocol used
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR2          FRF           LL_SPI_SetStandard
-  * @param  SPIx SPI Instance
-  * @param  Standard This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
-  *         @arg @ref LL_SPI_PROTOCOL_TI
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
-  MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
-}
-
-/**
-  * @brief  Get serial protocol used
-  * @rmtoll CR2          FRF           LL_SPI_GetStandard
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
-  *         @arg @ref LL_SPI_PROTOCOL_TI
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
-}
-
-/**
-  * @brief  Set clock phase
-  * @note   This bit should not be changed when communication is ongoing.
-  *         This bit is not used in SPI TI mode.
-  * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
-  * @param  SPIx SPI Instance
-  * @param  ClockPhase This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_PHASE_1EDGE
-  *         @arg @ref LL_SPI_PHASE_2EDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
-}
-
-/**
-  * @brief  Get clock phase
-  * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_PHASE_1EDGE
-  *         @arg @ref LL_SPI_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
-}
-
-/**
-  * @brief  Set clock polarity
-  * @note   This bit should not be changed when communication is ongoing.
-  *         This bit is not used in SPI TI mode.
-  * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
-  * @param  SPIx SPI Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_POLARITY_LOW
-  *         @arg @ref LL_SPI_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
-}
-
-/**
-  * @brief  Get clock polarity
-  * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_POLARITY_LOW
-  *         @arg @ref LL_SPI_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
-}
-
-/**
-  * @brief  Set baud rate prescaler
-  * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
-  * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
-  * @param  SPIx SPI Instance
-  * @param  BaudRate This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
-}
-
-/**
-  * @brief  Get baud rate prescaler
-  * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
-  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
-}
-
-/**
-  * @brief  Set transfer bit order
-  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
-  * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
-  * @param  SPIx SPI Instance
-  * @param  BitOrder This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_LSB_FIRST
-  *         @arg @ref LL_SPI_MSB_FIRST
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
-}
-
-/**
-  * @brief  Get transfer bit order
-  * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_LSB_FIRST
-  *         @arg @ref LL_SPI_MSB_FIRST
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
-}
-
-/**
-  * @brief  Set transfer direction mode
-  * @note   For Half-Duplex mode, Rx Direction is set by default.
-  *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
-  * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
-  *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
-  *         CR1          BIDIOE        LL_SPI_SetTransferDirection
-  * @param  SPIx SPI Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_FULL_DUPLEX
-  *         @arg @ref LL_SPI_SIMPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
-}
-
-/**
-  * @brief  Get transfer direction mode
-  * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
-  *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
-  *         CR1          BIDIOE        LL_SPI_GetTransferDirection
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_FULL_DUPLEX
-  *         @arg @ref LL_SPI_SIMPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_RX
-  *         @arg @ref LL_SPI_HALF_DUPLEX_TX
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
-}
-
-/**
-  * @brief  Set frame data width
-  * @rmtoll CR2          DS            LL_SPI_SetDataWidth
-  * @param  SPIx SPI Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
-{
-  MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
-}
-
-/**
-  * @brief  Get frame data width
-  * @rmtoll CR2          DS            LL_SPI_GetDataWidth
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_DATAWIDTH_4BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_5BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_6BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_7BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_8BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_9BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_10BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_11BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_12BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_13BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_14BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_15BIT
-  *         @arg @ref LL_SPI_DATAWIDTH_16BIT
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
-}
-
-/**
-  * @brief  Set threshold of RXFIFO that triggers an RXNE event
-  * @rmtoll CR2          FRXTH         LL_SPI_SetRxFIFOThreshold
-  * @param  SPIx SPI Instance
-  * @param  Threshold This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
-  *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
-{
-  MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
-}
-
-/**
-  * @brief  Get threshold of RXFIFO that triggers an RXNE event
-  * @rmtoll CR2          FRXTH         LL_SPI_GetRxFIFOThreshold
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_RX_FIFO_TH_HALF
-  *         @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_CRC_Management CRC Management
-  * @{
-  */
-
-/**
-  * @brief  Enable CRC
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
-  * @brief  Disable CRC
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
-  * @brief  Check if CRC is enabled
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set CRC Length
-  * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
-  * @rmtoll CR1          CRCL          LL_SPI_SetCRCWidth
-  * @param  SPIx SPI Instance
-  * @param  CRCLength This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_CRC_8BIT
-  *         @arg @ref LL_SPI_CRC_16BIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
-}
-
-/**
-  * @brief  Get CRC Length
-  * @rmtoll CR1          CRCL          LL_SPI_GetCRCWidth
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_CRC_8BIT
-  *         @arg @ref LL_SPI_CRC_16BIT
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
-}
-
-/**
-  * @brief  Set CRCNext to transfer CRC on the line
-  * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
-  * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
-}
-
-/**
-  * @brief  Set polynomial for CRC calculation
-  * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
-  * @param  SPIx SPI Instance
-  * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
-{
-  WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
-}
-
-/**
-  * @brief  Get polynomial for CRC calculation
-  * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
-  * @param  SPIx SPI Instance
-  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_REG(SPIx->CRCPR));
-}
-
-/**
-  * @brief  Get Rx CRC
-  * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
-  * @param  SPIx SPI Instance
-  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_REG(SPIx->RXCRCR));
-}
-
-/**
-  * @brief  Get Tx CRC
-  * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
-  * @param  SPIx SPI Instance
-  * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_REG(SPIx->TXCRCR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
-  * @{
-  */
-
-/**
-  * @brief  Set NSS mode
-  * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
-  * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
-  * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
-  * @param  SPIx SPI Instance
-  * @param  NSS This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_NSS_SOFT
-  *         @arg @ref LL_SPI_NSS_HARD_INPUT
-  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
-{
-  MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
-  MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
-}
-
-/**
-  * @brief  Get NSS mode
-  * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
-  * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_NSS_SOFT
-  *         @arg @ref LL_SPI_NSS_HARD_INPUT
-  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
-{
-  uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
-  uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
-  return (Ssm | Ssoe);
-}
-
-/**
-  * @brief  Enable NSS pulse management
-  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
-  * @rmtoll CR2          NSSP          LL_SPI_EnableNSSPulseMgt
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
-}
-
-/**
-  * @brief  Disable NSS pulse management
-  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
-  * @rmtoll CR2          NSSP          LL_SPI_DisableNSSPulseMgt
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
-}
-
-/**
-  * @brief  Check if NSS pulse is enabled
-  * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
-  * @rmtoll CR2          NSSP          LL_SPI_IsEnabledNSSPulse
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Check if Rx buffer is not empty
-  * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Tx buffer is empty
-  * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get CRC error flag
-  * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get mode fault error flag
-  * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get overrun error flag
-  * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get busy flag
-  * @note   The BSY flag is cleared under any one of the following conditions:
-  * -When the SPI is correctly disabled
-  * -When a fault is detected in Master mode (MODF bit set to 1)
-  * -In Master mode, when it finishes a data transmission and no new data is ready to be
-  * sent
-  * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
-  * each data transfer.
-  * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get frame format error flag
-  * @rmtoll SR           FRE           LL_SPI_IsActiveFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get FIFO reception Level
-  * @rmtoll SR           FRLVL         LL_SPI_GetRxFIFOLevel
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_RX_FIFO_EMPTY
-  *         @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
-  *         @arg @ref LL_SPI_RX_FIFO_HALF_FULL
-  *         @arg @ref LL_SPI_RX_FIFO_FULL
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
-}
-
-/**
-  * @brief  Get FIFO Transmission Level
-  * @rmtoll SR           FTLVL         LL_SPI_GetTxFIFOLevel
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_TX_FIFO_EMPTY
-  *         @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
-  *         @arg @ref LL_SPI_TX_FIFO_HALF_FULL
-  *         @arg @ref LL_SPI_TX_FIFO_FULL
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
-}
-
-/**
-  * @brief  Clear CRC error flag
-  * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
-}
-
-/**
-  * @brief  Clear mode fault error flag
-  * @note   Clearing this flag is done by a read access to the SPIx_SR
-  *         register followed by a write access to the SPIx_CR1 register
-  * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg_sr;
-  tmpreg_sr = SPIx->SR;
-  (void) tmpreg_sr;
-  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
-  * @brief  Clear overrun error flag
-  * @note   Clearing this flag is done by a read access to the SPIx_DR
-  *         register followed by a read access to the SPIx_SR register
-  * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = SPIx->DR;
-  (void) tmpreg;
-  tmpreg = SPIx->SR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear frame format error flag
-  * @note   Clearing this flag is done by reading SPIx_SR register
-  * @rmtoll SR           FRE           LL_SPI_ClearFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = SPIx->SR;
-  (void) tmpreg;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
-  * @{
-  */
-
-/**
-  * @brief  Enable error interrupt
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
-  * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
-  * @brief  Enable Rx buffer not empty interrupt
-  * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
-  * @brief  Enable Tx buffer empty interrupt
-  * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
-  * @brief  Disable error interrupt
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
-  * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
-  * @brief  Disable Rx buffer not empty interrupt
-  * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
-  * @brief  Disable Tx buffer empty interrupt
-  * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
-  * @brief  Check if error interrupt is enabled
-  * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Rx buffer not empty interrupt is enabled
-  * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if Tx buffer empty interrupt
-  * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_DMA_Management DMA Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA Rx is enabled
-  * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
-  * @brief  Disable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
-  * @brief  Check if DMA Tx is enabled
-  * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set parity of  Last DMA reception
-  * @rmtoll CR2          LDMARX        LL_SPI_SetDMAParity_RX
-  * @param  SPIx SPI Instance
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_DMA_PARITY_ODD
-  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
-{
-  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
-}
-
-/**
-  * @brief  Get parity configuration for  Last DMA reception
-  * @rmtoll CR2          LDMARX        LL_SPI_GetDMAParity_RX
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_DMA_PARITY_ODD
-  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
-}
-
-/**
-  * @brief  Set parity of  Last DMA transmission
-  * @rmtoll CR2          LDMATX        LL_SPI_SetDMAParity_TX
-  * @param  SPIx SPI Instance
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_SPI_DMA_PARITY_ODD
-  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
-{
-  MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
-}
-
-/**
-  * @brief  Get parity configuration for Last DMA transmission
-  * @rmtoll CR2          LDMATX        LL_SPI_GetDMAParity_TX
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SPI_DMA_PARITY_ODD
-  *         @arg @ref LL_SPI_DMA_PARITY_EVEN
-  */
-__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
-  * @param  SPIx SPI Instance
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
-{
-  return (uint32_t) &(SPIx->DR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EF_DATA_Management DATA Management
-  * @{
-  */
-
-/**
-  * @brief  Read 8-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_ReceiveData8
-  * @param  SPIx SPI Instance
-  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
-{
-  return (*((__IO uint8_t *)&SPIx->DR));
-}
-
-/**
-  * @brief  Read 16-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_ReceiveData16
-  * @param  SPIx SPI Instance
-  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
-{
-  return (uint16_t)(READ_REG(SPIx->DR));
-}
-
-/**
-  * @brief  Write 8-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_TransmitData8
-  * @param  SPIx SPI Instance
-  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
-{
-#if defined (__GNUC__)
-  __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
-  *spidr = TxData;
-#else
-  *((__IO uint8_t *)&SPIx->DR) = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
-  * @brief  Write 16-Bits in the data register
-  * @rmtoll DR           DR            LL_SPI_TransmitData16
-  * @param  SPIx SPI Instance
-  * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
-#if defined (__GNUC__)
-  __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
-  *spidr = TxData;
-#else
-  SPIx->DR = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
-void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup I2S_LL I2S
-  * @{
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  I2S Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t Mode;                    /*!< Specifies the I2S operating mode.
-                                         This parameter can be a value of @ref I2S_LL_EC_MODE
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
-
-  uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
-                                         This parameter can be a value of @ref I2S_LL_EC_STANDARD
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
-
-
-  uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
-                                         This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
-
-
-  uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                         This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
-
-                                         This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
-
-
-  uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
-                                         This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
-
-                                         Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
-                                         and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
-
-
-  uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
-                                         This parameter can be a value of @ref I2S_LL_EC_POLARITY
-
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
-
-} LL_I2S_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
-  * @{
-  */
-
-/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_I2S_ReadReg function
-  * @{
-  */
-#define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
-#define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
-#define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
-#define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
-#define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
-#define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
-  * @{
-  */
-#define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
-#define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
-#define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
-  * @{
-  */
-#define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel length 16bit */
-#define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel length 32bit */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
-#define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_STANDARD I2s Standard
-  * @{
-  */
-#define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
-#define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
-#define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
-#define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
-#define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_MODE Operation Mode
-  * @{
-  */
-#define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
-#define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
-#define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
-#define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
-  * @{
-  */
-#define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
-#define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
-  * @{
-  */
-#define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
-#define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
-  * @{
-  */
-
-#define LL_I2S_AUDIOFREQ_192K              192000U       /*!< Audio Frequency configuration 192000 Hz       */
-#define LL_I2S_AUDIOFREQ_96K               96000U        /*!< Audio Frequency configuration  96000 Hz       */
-#define LL_I2S_AUDIOFREQ_48K               48000U        /*!< Audio Frequency configuration  48000 Hz       */
-#define LL_I2S_AUDIOFREQ_44K               44100U        /*!< Audio Frequency configuration  44100 Hz       */
-#define LL_I2S_AUDIOFREQ_32K               32000U        /*!< Audio Frequency configuration  32000 Hz       */
-#define LL_I2S_AUDIOFREQ_22K               22050U        /*!< Audio Frequency configuration  22050 Hz       */
-#define LL_I2S_AUDIOFREQ_16K               16000U        /*!< Audio Frequency configuration  16000 Hz       */
-#define LL_I2S_AUDIOFREQ_11K               11025U        /*!< Audio Frequency configuration  11025 Hz       */
-#define LL_I2S_AUDIOFREQ_8K                8000U         /*!< Audio Frequency configuration   8000 Hz       */
-#define LL_I2S_AUDIOFREQ_DEFAULT           2U            /*!< Audio Freq not specified. Register I2SDIV = 2 */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
-  * @{
-  */
-
-/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in I2S register
-  * @param  __INSTANCE__ I2S Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in I2S register
-  * @param  __INSTANCE__ I2S Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @defgroup I2S_LL_EF_Configuration Configuration
-  * @{
-  */
-
-/**
-  * @brief  Select I2S mode and Enable I2S peripheral
-  * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
-  *         I2SCFGR      I2SE          LL_I2S_Enable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
-  * @brief  Disable I2S peripheral
-  * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
-  * @brief  Check if I2S peripheral is enabled
-  * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set I2S data frame length
-  * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
-  *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
-  * @param  SPIx SPI Instance
-  * @param  DataFormat This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_DATAFORMAT_16B
-  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
-  *         @arg @ref LL_I2S_DATAFORMAT_24B
-  *         @arg @ref LL_I2S_DATAFORMAT_32B
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
-{
-  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
-}
-
-/**
-  * @brief  Get I2S data frame length
-  * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
-  *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_DATAFORMAT_16B
-  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
-  *         @arg @ref LL_I2S_DATAFORMAT_24B
-  *         @arg @ref LL_I2S_DATAFORMAT_32B
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
-}
-
-/**
-  * @brief  Set I2S clock polarity
-  * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
-  * @param  SPIx SPI Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_POLARITY_LOW
-  *         @arg @ref LL_I2S_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
-  SET_BIT(SPIx->I2SCFGR, ClockPolarity);
-}
-
-/**
-  * @brief  Get I2S clock polarity
-  * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_POLARITY_LOW
-  *         @arg @ref LL_I2S_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
-}
-
-/**
-  * @brief  Set I2S standard protocol
-  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
-  *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
-  * @param  SPIx SPI Instance
-  * @param  Standard This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_STANDARD_PHILIPS
-  *         @arg @ref LL_I2S_STANDARD_MSB
-  *         @arg @ref LL_I2S_STANDARD_LSB
-  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
-  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
-  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
-}
-
-/**
-  * @brief  Get I2S standard protocol
-  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
-  *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_STANDARD_PHILIPS
-  *         @arg @ref LL_I2S_STANDARD_MSB
-  *         @arg @ref LL_I2S_STANDARD_LSB
-  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
-  *         @arg @ref LL_I2S_STANDARD_PCM_LONG
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
-}
-
-/**
-  * @brief  Set I2S transfer mode
-  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
-  * @param  SPIx SPI Instance
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_MODE_SLAVE_TX
-  *         @arg @ref LL_I2S_MODE_SLAVE_RX
-  *         @arg @ref LL_I2S_MODE_MASTER_TX
-  *         @arg @ref LL_I2S_MODE_MASTER_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
-  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
-}
-
-/**
-  * @brief  Get I2S transfer mode
-  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_MODE_SLAVE_TX
-  *         @arg @ref LL_I2S_MODE_SLAVE_RX
-  *         @arg @ref LL_I2S_MODE_MASTER_TX
-  *         @arg @ref LL_I2S_MODE_MASTER_RX
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
-}
-
-/**
-  * @brief  Set I2S linear prescaler
-  * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
-  * @param  SPIx SPI Instance
-  * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
-{
-  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
-}
-
-/**
-  * @brief  Get I2S linear prescaler
-  * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
-  * @param  SPIx SPI Instance
-  * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
-}
-
-/**
-  * @brief  Set I2S parity prescaler
-  * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
-  * @param  SPIx SPI Instance
-  * @param  PrescalerParity This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
-{
-  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
-}
-
-/**
-  * @brief  Get I2S parity prescaler
-  * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
-  * @param  SPIx SPI Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
-{
-  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
-}
-
-/**
-  * @brief  Enable the master clock output (Pin MCK)
-  * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
-  * @brief  Disable the master clock output (Pin MCK)
-  * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
-  * @brief  Check if the master clock output (Pin MCK) is enabled
-  * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
-}
-
-#if defined(SPI_I2SCFGR_ASTRTEN)
-/**
-  * @brief  Enable asynchronous start
-  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_EnableAsyncStart
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
-{
-  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
-}
-
-/**
-  * @brief  Disable  asynchronous start
-  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_DisableAsyncStart
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
-{
-  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
-}
-
-/**
-  * @brief  Check if asynchronous start is enabled
-  * @rmtoll I2SCFGR      ASTRTEN       LL_I2S_IsEnabledAsyncStart
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
-}
-#endif /* SPI_I2SCFGR_ASTRTEN */
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_FLAG FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Check if Rx buffer is not empty
-  * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_RXNE(SPIx);
-}
-
-/**
-  * @brief  Check if Tx buffer is empty
-  * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_TXE(SPIx);
-}
-
-/**
-  * @brief  Get busy flag
-  * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_BSY(SPIx);
-}
-
-/**
-  * @brief  Get overrun error flag
-  * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_OVR(SPIx);
-}
-
-/**
-  * @brief  Get underrun error flag
-  * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get frame format error flag
-  * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsActiveFlag_FRE(SPIx);
-}
-
-/**
-  * @brief  Get channel side flag.
-  * @note   0: Channel Left has to be transmitted or has been received\n
-  *         1: Channel Right has to be transmitted or has been received\n
-  *         It has no significance in PCM mode.
-  * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
-{
-  return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear overrun error flag
-  * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
-  LL_SPI_ClearFlag_OVR(SPIx);
-}
-
-/**
-  * @brief  Clear underrun error flag
-  * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = SPIx->SR;
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Clear frame format error flag
-  * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_ClearFlag_FRE(SPIx);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_IT Interrupt Management
-  * @{
-  */
-
-/**
-  * @brief  Enable error IT
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
-  * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableIT_ERR(SPIx);
-}
-
-/**
-  * @brief  Enable Rx buffer not empty IT
-  * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableIT_RXNE(SPIx);
-}
-
-/**
-  * @brief  Enable Tx buffer empty IT
-  * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableIT_TXE(SPIx);
-}
-
-/**
-  * @brief  Disable error IT
-  * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
-  * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableIT_ERR(SPIx);
-}
-
-/**
-  * @brief  Disable Rx buffer not empty IT
-  * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableIT_RXNE(SPIx);
-}
-
-/**
-  * @brief  Disable Tx buffer empty IT
-  * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableIT_TXE(SPIx);
-}
-
-/**
-  * @brief  Check if ERR IT is enabled
-  * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledIT_ERR(SPIx);
-}
-
-/**
-  * @brief  Check if RXNE IT is enabled
-  * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledIT_RXNE(SPIx);
-}
-
-/**
-  * @brief  Check if TXE IT is enabled
-  * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledIT_TXE(SPIx);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_DMA DMA Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableDMAReq_RX(SPIx);
-}
-
-/**
-  * @brief  Disable DMA Rx
-  * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableDMAReq_RX(SPIx);
-}
-
-/**
-  * @brief  Check if DMA Rx is enabled
-  * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledDMAReq_RX(SPIx);
-}
-
-/**
-  * @brief  Enable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_EnableDMAReq_TX(SPIx);
-}
-
-/**
-  * @brief  Disable DMA Tx
-  * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  LL_SPI_DisableDMAReq_TX(SPIx);
-}
-
-/**
-  * @brief  Check if DMA Tx is enabled
-  * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
-  * @param  SPIx SPI Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_IsEnabledDMAReq_TX(SPIx);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_LL_EF_DATA DATA Management
-  * @{
-  */
-
-/**
-  * @brief  Read 16-Bits in data register
-  * @rmtoll DR           DR            LL_I2S_ReceiveData16
-  * @param  SPIx SPI Instance
-  * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_ReceiveData16(SPIx);
-}
-
-/**
-  * @brief  Write 16-Bits in data register
-  * @rmtoll DR           DR            LL_I2S_TransmitData16
-  * @param  SPIx SPI Instance
-  * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
-  LL_SPI_TransmitData16(SPIx, TxData);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
-void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
-void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_system.h

@@ -1,2084 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_system.h
-  * @author  MCD Application Team
-  * @brief   Header file of SYSTEM LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL SYSTEM driver contains a set of generic APIs that can be
-    used by user:
-      (+) Some of the FLASH features need to be handled in the SYSTEM file.
-      (+) Access to DBG registers
-      (+) Access to SYSCFG registers
-      (+) Access to VREFBUF registers
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_SYSTEM_H
-#define STM32G0xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (FLASH) || defined (SYSCFG) || defined (DBG)
-
-/** @defgroup SYSTEM_LL SYSTEM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
-  * @{
-  */
-#define LL_SYSCFG_REMAP_FLASH               0x00000000U                                           /*!< Main Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SYSTEMFLASH         SYSCFG_CFGR1_MEM_MODE_0                               /*!< System Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SRAM                (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)   /*!< Embedded SRAM mapped at 0x00000000 */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_PIN_RMP SYSCFG PIN RMP
-  * @{
-  */
-#define LL_SYSCFG_PIN_RMP_PA11              SYSCFG_CFGR1_PA11_RMP                           /*!< PA11 pad behaves as PA9 pin */
-#define LL_SYSCFG_PIN_RMP_PA12              SYSCFG_CFGR1_PA12_RMP                           /*!< PA12 pad behaves as PA10 pin */
-/**
-  * @}
-  */
-
-
-#if defined(SYSCFG_CFGR1_IR_MOD)
-/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
-  * @{
-  */
-#define LL_SYSCFG_IR_MOD_TIM16       (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)    /*!< 00: Timer16 is selected as IRDA Modulation enveloppe source */
-#define LL_SYSCFG_IR_MOD_USART1      (SYSCFG_CFGR1_IR_MOD_0)                            /*!< 01: USART1 is selected as IRDA Modulation enveloppe source */
-#if defined(USART4)
-#define LL_SYSCFG_IR_MOD_USART4      (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART4 is selected as IRDA Modulation enveloppe source */
-#else  
-#define LL_SYSCFG_IR_MOD_USART2      (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART2 is selected as IRDA Modulation enveloppe source */
-#endif /* USART4 */
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_EC_IR_POL SYSCFG IR Polarity
-  * @{
-  */
-#define LL_SYSCFG_IR_POL_NOT_INVERTED  0x00000000U                                     /*!< 0: Output of IRDA (IROut) not inverted */
-#define LL_SYSCFG_IR_POL_INVERTED     (SYSCFG_CFGR1_IR_POL)                            /*!< 1: Output of IRDA (IROut) inverted */
-/**
-  * @}
-  */
-#endif /* SYSCFG_CFGR1_IR_MOD */
-
-#if defined(SYSCFG_CFGR1_BOOSTEN)
-/** @defgroup SYSTEM_LL_EC_BOOSTEN SYSCFG I/O analog switch voltage booster enable
-  * @{
-  */
-#define LL_SYSCFG_CFGR1_BOOSTEN       SYSCFG_CFGR1_BOOSTEN                             /*!< I/O analog switch voltage booster enable */
-/**
-  * @}
-  */
-#endif /* SYSCFG_CFGR1_BOOSTEN */
-
-#if defined(SYSCFG_CFGR1_UCPD1_STROBE) ||  defined(SYSCFG_CFGR1_UCPD2_STROBE)
-/** @defgroup SYSTEM_LL_EC_UCPD_DBATTDIS SYSCFG UCPD Dead Battery feature Disable
-  * @{
-  */
-#define LL_SYSCFG_UCPD1_STROBE       SYSCFG_CFGR1_UCPD1_STROBE       /*!< UCPD1 STROBE sw configuration */
-#define LL_SYSCFG_UCPD2_STROBE       SYSCFG_CFGR1_UCPD2_STROBE       /*!< UCPD2 STROBE sw configuration */
-/**
-  * @}
-  */
-#endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */
-
-/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
-  * @{
-  */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< I2C PB6 Fast mode plus */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< I2C PB7 Fast mode plus */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< I2C PB8 Fast mode plus */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< I2C PB9 Fast mode plus */
-#if defined(SYSCFG_CFGR1_I2C1_FMP)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP /*!< Enable I2C1 Fast mode Plus  */
-#endif /*SYSCFG_CFGR1_I2C1_FMP*/
-#if defined(SYSCFG_CFGR1_I2C2_FMP)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP /*!< Enable I2C2 Fast mode plus  */
-#endif /*SYSCFG_CFGR1_I2C2_FMP*/
-#if defined(SYSCFG_CFGR1_I2C_PA9_FMP)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9     SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9  */
-#endif /*SYSCFG_CFGR1_I2C_PA9_FMP*/
-#if defined(SYSCFG_CFGR1_I2C_PA10_FMP)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10    SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */
-#endif /*SYSCFG_CFGR1_I2C_PA10_FMP*/
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#if defined(SYSCFG_CFGR1_I2C3_FMP)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP /*!< Enable I2C3 Fast mode plus  */
-#endif /*SYSCFG_CFGR1_I2C3_FMP*/
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
-  * @{
-  */
-#define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL            /*!< Enables and locks the ECC error signal
-                                                                           with Break Input of TIM1/15/16/17 */
-#if defined (PWR_PVD_SUPPORT)
-#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL           /*!< Enables and locks the PVD connection
-                                                                       with TIM1/15/16/17 Break Input and also
-                                                                       the PVDE and PLS bits of the Power Control Interface */
-#endif /* PWR_PVD_SUPPORT */
-#define LL_SYSCFG_TIMBREAK_SRAM_PARITY     SYSCFG_CFGR2_SPL            /*!< Enables and locks the SRAM_PARITY error signal
-                                                                                with Break Input of TIM1/15/16/17 */
-#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL            /*!< Enables and locks the LOCKUP (Hardfault) output of
-                                                                           CortexM0 with Break Input of TIM1/15/16/17 */
-/**
-  * @}
-  */
-
-#if defined(SYSCFG_CDEN_SUPPORT)
-/** @defgroup SYSTEM_LL_EC_CLAMPING_DIODE SYSCFG CLAMPING DIODE
-  * @{
-  */  
-#define LL_SYSCFG_CFGR2_PA1_CDEN         SYSCFG_CFGR2_PA1_CDEN     /*!< Enables Clamping diode of PA1 */
-#define LL_SYSCFG_CFGR2_PA3_CDEN         SYSCFG_CFGR2_PA3_CDEN     /*!< Enables Clamping diode of PA3 */
-#define LL_SYSCFG_CFGR2_PA5_CDEN         SYSCFG_CFGR2_PA5_CDEN     /*!< Enables Clamping diode of PA5 */
-#define LL_SYSCFG_CFGR2_PA6_CDEN         SYSCFG_CFGR2_PA6_CDEN     /*!< Enables Clamping diode of PA6 */
-#define LL_SYSCFG_CFGR2_PA13_CDEN        SYSCFG_CFGR2_PA13_CDEN    /*!< Enables Clamping diode of PA13 */
-#define LL_SYSCFG_CFGR2_PB0_CDEN         SYSCFG_CFGR2_PB0_CDEN     /*!< Enables Clamping diode of PB0 */
-#define LL_SYSCFG_CFGR2_PB1_CDEN         SYSCFG_CFGR2_PB1_CDEN     /*!< Enables Clamping diode of PB1 */  
-#define LL_SYSCFG_CFGR2_PB2_CDEN         SYSCFG_CFGR2_PB2_CDEN     /*!< Enables Clamping diode of PB2 */
-/**
-  * @}
-  */
-#endif /* SYSCFG_CDEN_SUPPORT */
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP  DBGMCU APB1 GRP1 STOP IP
-  * @{
-  */
-#if defined(DBG_APB_FZ1_DBG_TIM2_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBG_APB_FZ1_DBG_TIM2_STOP        /*!< TIM2 counter stopped when core is halted */
-#endif /*DBG_APB_FZ1_DBG_TIM2_STOP*/
-#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBG_APB_FZ1_DBG_TIM3_STOP        /*!< TIM3 counter stopped when core is halted */
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBG_APB_FZ1_DBG_TIM4_STOP        /*!< TIM4 counter stopped when core is halted */
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-#if defined(DBG_APB_FZ1_DBG_TIM6_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBG_APB_FZ1_DBG_TIM6_STOP        /*!< TIM6 counter stopped when core is halted */
-#endif /*DBG_APB_FZ1_DBG_TIM6_STOP*/
-#if defined(DBG_APB_FZ1_DBG_TIM7_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBG_APB_FZ1_DBG_TIM7_STOP        /*!< TIM7 counter stopped when core is halted  */
-#endif /*DBG_APB_FZ1_DBG_TIM7_STOP*/
-#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBG_APB_FZ1_DBG_RTC_STOP         /*!< RTC Calendar frozen when core is halted */
-#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBG_APB_FZ1_DBG_WWDG_STOP        /*!< Debug Window Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBG_APB_FZ1_DBG_IWDG_STOP        /*!< Debug Independent Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-#if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP)
-#define LL_DBGMCU_APB1_GRP1_LPTIM2_STOP    DBG_APB_FZ1_DBG_LPTIM2_STOP      /*!< LPTIM2 counter stopped when Core is halted */
-#endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */
-#if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP)
-#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBG_APB_FZ1_DBG_LPTIM1_STOP      /*!< LPTIM1 counter stopped when Core is halted */
-#endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
-  * @{
-  */
-#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBG_APB_FZ2_DBG_TIM1_STOP        /*!< TIM1 counter stopped when core is halted */
-#if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM14_STOP     DBG_APB_FZ2_DBG_TIM14_STOP       /*!< TIM14 counter stopped when core is halted */
-#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
-#if defined(DBG_APB_FZ2_DBG_TIM15_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBG_APB_FZ2_DBG_TIM15_STOP       /*!< TIM15 counter stopped when core is halted  */
-#endif /*DBG_APB_FZ2_DBG_TIM15_STOP*/
-#define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBG_APB_FZ2_DBG_TIM16_STOP       /*!< TIM16 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBG_APB_FZ2_DBG_TIM17_STOP       /*!< TIM17 counter stopped when core is halted */
-/**
-  * @}
-  */
-
-
-#if defined(VREFBUF)
-/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
-  * @{
-  */
-#define LL_VREFBUF_VOLTAGE_SCALE0          0x00000000U            /*!< Voltage reference scale 0 (VREF_OUT1) */
-#define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
-/**
-  * @}
-  */
-#endif /* VREFBUF */
-
-/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
-  * @{
-  */
-#define LL_FLASH_LATENCY_0                 0x00000000U             /*!< FLASH Zero Latency cycle */
-#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_0     /*!< FLASH One Latency cycle */
-#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_1     /*!< FLASH Two wait states */
-#define LL_FLASH_LATENCY_3                 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)     /*!< FLASH Three wait states */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
-  * @{
-  */
-
-/**
-  * @brief  Set memory mapping at address 0x00000000
-  * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_SetRemapMemory
-  * @param  Memory This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_REMAP_FLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SRAM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
-{
-  MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
-}
-
-/**
-  * @brief  Get memory mapping at address 0x00000000
-  * @rmtoll SYSCFG_CFGR1 MEM_MODE      LL_SYSCFG_GetRemapMemory
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_REMAP_FLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SRAM
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
-}
-
-/**
-  * @brief  Enable remap of a pin on different pad
-  * @rmtoll SYSCFG_CFGR1 PA11_RMP  LL_SYSCFG_EnablePinRemap\n
-  *         SYSCFG_CFGR1 PA12_RMP   LL_SYSCFG_EnablePinRemap\n
-  * @param  PinRemap This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_PIN_RMP_PA11
-  *         @arg @ref LL_SYSCFG_PIN_RMP_PA12
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(uint32_t PinRemap)
-{
-  SET_BIT(SYSCFG->CFGR1, PinRemap);
-}
-
-/**
-  * @brief  Enable remap of a pin on different pad
-  * @rmtoll SYSCFG_CFGR1 PA11_RMP  LL_SYSCFG_DisablePinRemap\n
-  *         SYSCFG_CFGR1 PA12_RMP   LL_SYSCFG_DisablePinRemap\n
-  * @param  PinRemap This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_PIN_RMP_PA11
-  *         @arg @ref LL_SYSCFG_PIN_RMP_PA12
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(uint32_t PinRemap)
-{
-  CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
-}
-
-#if defined(SYSCFG_CFGR1_IR_MOD)
-/**
-  * @brief  Set IR Modulation Envelope signal source.
-  * @rmtoll SYSCFG_CFGR1 IR_MOD  LL_SYSCFG_SetIRModEnvelopeSignal
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_IR_MOD_TIM16
-  *         @arg @ref LL_SYSCFG_IR_MOD_USART1
-  *         @arg @ref LL_SYSCFG_IR_MOD_USART4
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
-}
-
-/**
-  * @brief  Get IR Modulation Envelope signal source.
-  * @rmtoll SYSCFG_CFGR1 IR_MOD  LL_SYSCFG_GetIRModEnvelopeSignal
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_IR_MOD_TIM16
-  *         @arg @ref LL_SYSCFG_IR_MOD_USART1
-  *         @arg @ref LL_SYSCFG_IR_MOD_USART4
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
-}
-
-/**
-  * @brief  Set IR Output polarity.
-  * @rmtoll SYSCFG_CFGR1 IR_POL  LL_SYSCFG_SetIRPolarity
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_IR_POL_INVERTED
-  *         @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetIRPolarity(uint32_t Polarity)
-{
-  MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL, Polarity);
-}
-
-/**
-  * @brief  Get IR Output polarity.
-  * @rmtoll SYSCFG_CFGR1 IR_POL  LL_SYSCFG_GetIRPolarity
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_IR_POL_INVERTED
-  *         @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetIRPolarity(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL));
-}
-#endif /* SYSCFG_CFGR1_IR_MOD */
-
-#if defined(SYSCFG_CFGR1_BOOSTEN)
-/**
-  * @brief  Enable I/O analog switch voltage booster.
-  * @note   When voltage booster is enabled, I/O analog switches are supplied
-  *         by a dedicated voltage booster, from VDD power domain. This is
-  *         the recommended configuration with low VDDA voltage operation.
-  * @note   The I/O analog switch voltage booster is relevant for peripherals
-  *         using I/O in analog input: ADC, COMP.
-  *         However, COMP and OPAMP inputs have a high impedance and
-  *         voltage booster do not impact performance significantly.
-  *         Therefore, the voltage booster is mainly intended for
-  *         usage with ADC.
-  * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
-{
-  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-
-/**
-  * @brief  Disable I/O analog switch voltage booster.
-  * @note   When voltage booster is enabled, I/O analog switches are supplied
-  *         by a dedicated voltage booster, from VDD power domain. This is
-  *         the recommended configuration with low VDDA voltage operation.
-  * @note   The I/O analog switch voltage booster is relevant for peripherals
-  *         using I/O in analog input: ADC, COMP.
-  *         However, COMP and OPAMP inputs have a high impedance and
-  *         voltage booster do not impact performance significantly.
-  *         Therefore, the voltage booster is mainly intended for
-  *         usage with ADC.
-  * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
-{
-  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
-}
-#endif /* SYSCFG_CFGR1_BOOSTEN */
-
-/**
-  * @brief  Enable the I2C fast mode plus driving capability.
-  * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6   LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_PB7   LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_PB8   LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_PB9   LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_I2C1  LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_I2C2  LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_I2C3  LL_SYSCFG_EnableFastModePlus\n  
-  *         SYSCFG_CFGR1 I2C_FMP_PA9   LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_PA10  LL_SYSCFG_EnableFastModePlus
-  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)  
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
-}
-
-/**
-  * @brief  Disable the I2C fast mode plus driving capability.
-  * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6   LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_PB7   LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_PB8   LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_PB9   LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_I2C1  LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_I2C2  LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_I2C3  LL_SYSCFG_DisableFastModePlus\n  
-  *         SYSCFG_CFGR1 I2C_FMP_PA9   LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_CFGR1 I2C_FMP_PA10  LL_SYSCFG_DisableFastModePlus
-  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
-}
-
-#if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
-/**
-  * @brief  Disable dead battery behavior
-  * @rmtoll SYSCFG_CFGR1 UCPD1_STROBE   LL_SYSCFG_DisableDBATT\n
-  *         SYSCFG_CFGR1 UCPD2_STROBE   LL_SYSCFG_DisableDBATT
-  * @param  ConfigDeadBattery This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_UCPD1_STROBE\n
-  *         @arg @ref LL_SYSCFG_UCPD2_STROBE
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableDBATT(uint32_t ConfigDeadBattery)
-{
-  SET_BIT(SYSCFG->CFGR1, ConfigDeadBattery);
-}
-#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
-
-#if defined(SYSCFG_ITLINE0_SR_EWDG)
-/**
-  * @brief  Check if Window watchdog interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE0 SR_EWDG       LL_SYSCFG_IsActiveFlag_WWDG
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE0_SR_EWDG */
-
-#if defined (PWR_PVD_SUPPORT)
-/**
-  * @brief  Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
-  * @rmtoll SYSCFG_ITLINE1 SR_PVDOUT     LL_SYSCFG_IsActiveFlag_PVDOUT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT)) ? 1UL : 0UL);
-}
-#endif /* PWR_PVD_SUPPORT */
-
-#if defined (PWR_PVM_SUPPORT)
-/**
-  * @brief  Check if VDDUSB supply monitoring interrupt occurred or not (EXTI line 34).
-  * @rmtoll SYSCFG_ITLINE1 SR_PVMOUT     LL_SYSCFG_IsActiveFlag_PVMOUT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVMOUT(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVMOUT) == (SYSCFG_ITLINE1_SR_PVMOUT)) ? 1UL : 0UL);
-}
-#endif /* PWR_PVM_SUPPORT */
-
-#if defined(SYSCFG_ITLINE2_SR_RTC)
-/**
-  * @brief  Check if RTC Wake Up interrupt occurred or not (EXTI line 19).
-  * @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP  LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC) == (SYSCFG_ITLINE2_SR_RTC)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE2_SR_RTC */
-
-#if defined(SYSCFG_ITLINE2_SR_TAMPER)
-/**
-  * @brief  Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 21).
-  * @rmtoll SYSCFG_ITLINE2 SR_TAMPER  LL_SYSCFG_IsActiveFlag_TAMPER
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TAMPER(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_TAMPER) == (SYSCFG_ITLINE2_SR_TAMPER)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE2_SR_TAMPER */
-
-#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
-/**
-  * @brief  Check if Flash interface interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF  LL_SYSCFG_IsActiveFlag_FLASH_ITF
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
-
-#if defined(SYSCFG_ITLINE3_SR_FLASH_ECC)
-/**
-  * @brief  Check if Flash interface interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ECC  LL_SYSCFG_IsActiveFlag_FLASH_ECC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ECC(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ECC) == (SYSCFG_ITLINE3_SR_FLASH_ECC)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE3_SR_FLASH_ECC */
-
-#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
-/**
-  * @brief  Check if Reset and clock control interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL   LL_SYSCFG_IsActiveFlag_CLK_CTRL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
-
-#if defined(CRS)
-/**
-  * @brief  Check if Reset and clock control interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE4 SR_CRS   LL_SYSCFG_IsActiveFlag_CRS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS)) ? 1UL : 0UL);
-}
-#endif /* CRS */
-#if defined(SYSCFG_ITLINE5_SR_EXTI0)
-/**
-  * @brief  Check if EXTI line 0 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE5 SR_EXTI0      LL_SYSCFG_IsActiveFlag_EXTI0
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE5_SR_EXTI0 */
-
-#if defined(SYSCFG_ITLINE5_SR_EXTI1)
-/**
-  * @brief  Check if EXTI line 1 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE5 SR_EXTI1      LL_SYSCFG_IsActiveFlag_EXTI1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE5_SR_EXTI1 */
-
-#if defined(SYSCFG_ITLINE6_SR_EXTI2)
-/**
-  * @brief  Check if EXTI line 2 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE6 SR_EXTI2      LL_SYSCFG_IsActiveFlag_EXTI2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE6_SR_EXTI2 */
-
-#if defined(SYSCFG_ITLINE6_SR_EXTI3)
-/**
-  * @brief  Check if EXTI line 3 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE6 SR_EXTI3      LL_SYSCFG_IsActiveFlag_EXTI3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE6_SR_EXTI3 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI4)
-/**
-  * @brief  Check if EXTI line 4 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI4      LL_SYSCFG_IsActiveFlag_EXTI4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI4 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI5)
-/**
-  * @brief  Check if EXTI line 5 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI5      LL_SYSCFG_IsActiveFlag_EXTI5
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI5 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI6)
-/**
-  * @brief  Check if EXTI line 6 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI6      LL_SYSCFG_IsActiveFlag_EXTI6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI6 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI7)
-/**
-  * @brief  Check if EXTI line 7 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI7      LL_SYSCFG_IsActiveFlag_EXTI7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI7 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI8)
-/**
-  * @brief  Check if EXTI line 8 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI8      LL_SYSCFG_IsActiveFlag_EXTI8
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI8 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI9)
-/**
-  * @brief  Check if EXTI line 9 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI9      LL_SYSCFG_IsActiveFlag_EXTI9
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI9 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI10)
-/**
-  * @brief  Check if EXTI line 10 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI10     LL_SYSCFG_IsActiveFlag_EXTI10
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI10 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI11)
-/**
-  * @brief  Check if EXTI line 11 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI11     LL_SYSCFG_IsActiveFlag_EXTI11
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI11 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI12)
-/**
-  * @brief  Check if EXTI line 12 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI12     LL_SYSCFG_IsActiveFlag_EXTI12
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI12 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI13)
-/**
-  * @brief  Check if EXTI line 13 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI13     LL_SYSCFG_IsActiveFlag_EXTI13
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI13 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI14)
-/**
-  * @brief  Check if EXTI line 14 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI14     LL_SYSCFG_IsActiveFlag_EXTI14
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI14 */
-
-#if defined(SYSCFG_ITLINE7_SR_EXTI15)
-/**
-  * @brief  Check if EXTI line 15 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE7 SR_EXTI15     LL_SYSCFG_IsActiveFlag_EXTI15
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE7_SR_EXTI15 */
-
-#if defined(SYSCFG_ITLINE8_SR_UCPD1)
-/**
-  * @brief  Check if UCPD1 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE8 SR_UCPD1    LL_SYSCFG_IsActiveFlag_UCPD1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_UCPD1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_UCPD1) == (SYSCFG_ITLINE8_SR_UCPD1)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE8_SR_UCPD1 */
-
-#if defined(SYSCFG_ITLINE8_SR_UCPD2)
-/**
-  * @brief  Check if UCPD2 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE8 SR_UCPD2    LL_SYSCFG_IsActiveFlag_UCPD2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_UCPD2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_UCPD2) == (SYSCFG_ITLINE8_SR_UCPD2)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE8_SR_UCPD2 */
-
-#if defined(SYSCFG_ITLINE8_SR_USB)
-/**
-  * @brief  Check if USB interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE8 SR_USB    LL_SYSCFG_IsActiveFlag_USB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USB(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_USB) == (SYSCFG_ITLINE8_SR_USB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE8_SR_USB */
-
-#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
-/**
-  * @brief  Check if DMA1 channel 1 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1   LL_SYSCFG_IsActiveFlag_DMA1_CH1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
-
-#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
-/**
-  * @brief  Check if DMA1 channel 2 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2   LL_SYSCFG_IsActiveFlag_DMA1_CH2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
-
-#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
-/**
-  * @brief  Check if DMA1 channel 3 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3   LL_SYSCFG_IsActiveFlag_DMA1_CH3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
-
-#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
-/**
-  * @brief  Check if DMA1 channel 4 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4   LL_SYSCFG_IsActiveFlag_DMA1_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
-
-#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
-/**
-  * @brief  Check if DMA1 channel 5 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5   LL_SYSCFG_IsActiveFlag_DMA1_CH5
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
-
-#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
-/**
-  * @brief  Check if DMA1 channel 6 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6   LL_SYSCFG_IsActiveFlag_DMA1_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
-
-#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
-/**
-  * @brief  Check if DMA1 channel 7 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7   LL_SYSCFG_IsActiveFlag_DMA1_CH7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
-
-#if defined(SYSCFG_ITLINE11_SR_DMAMUX1)
-/**
-  * @brief  Check if DMAMUX interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMAMUX1   LL_SYSCFG_IsActiveFlag_DMAMUX
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMAMUX(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMAMUX1) == (SYSCFG_ITLINE11_SR_DMAMUX1)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMAMUX */
-
-#if defined(SYSCFG_ITLINE11_SR_DMA2_CH1)
-/**
-  * @brief  Check if DMA2_CH1 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH1   LL_SYSCFG_IsActiveFlag_DMA2_CH1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH1) == (SYSCFG_ITLINE11_SR_DMA2_CH1)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMA2_CH1 */
-
-#if defined(SYSCFG_ITLINE11_SR_DMA2_CH2)
-/**
-  * @brief  Check if DMA2_CH2 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH2   LL_SYSCFG_IsActiveFlag_DMA2_CH2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH2) == (SYSCFG_ITLINE11_SR_DMA2_CH2)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMA2_CH2 */
-
-#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3)
-/**
-  * @brief  Check if DMA2_CH3 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3   LL_SYSCFG_IsActiveFlag_DMA2_CH3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */
-
-#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4)
-/**
-  * @brief  Check if DMA2_CH4 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4   LL_SYSCFG_IsActiveFlag_DMA2_CH4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */
-
-#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5)
-/**
-  * @brief  Check if DMA2_CH5 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5   LL_SYSCFG_IsActiveFlag_DMA2_CH5
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */
-
-#if defined(SYSCFG_ITLINE12_SR_ADC)
-/**
-  * @brief  Check if ADC interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE12 SR_ADC        LL_SYSCFG_IsActiveFlag_ADC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE12_SR_ADC */
-
-#if defined(SYSCFG_ITLINE12_SR_COMP1)
-/**
-  * @brief  Check if Comparator 1 interrupt occurred or not (EXTI line 21).
-  * @rmtoll SYSCFG_ITLINE12 SR_COMP1      LL_SYSCFG_IsActiveFlag_COMP1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE12_SR_COMP1 */
-
-#if defined(SYSCFG_ITLINE12_SR_COMP2)
-/**
-  * @brief  Check if Comparator 2 interrupt occurred or not (EXTI line 22).
-  * @rmtoll SYSCFG_ITLINE12 SR_COMP2      LL_SYSCFG_IsActiveFlag_COMP2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE12_SR_COMP2 */
-
-#if defined(SYSCFG_ITLINE12_SR_COMP3)
-/**
-  * @brief  Check if Comparator 3 interrupt occurred or not (EXTI line 20).
-  * @rmtoll SYSCFG_ITLINE12 SR_COMP3      LL_SYSCFG_IsActiveFlag_COMP3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP3(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP3) == (SYSCFG_ITLINE12_SR_COMP3)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE12_SR_COMP3 */
-
-#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
-/**
-  * @brief  Check if Timer 1 break interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK   LL_SYSCFG_IsActiveFlag_TIM1_BRK
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
-
-#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
-/**
-  * @brief  Check if Timer 1 update interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD   LL_SYSCFG_IsActiveFlag_TIM1_UPD
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
-
-#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
-/**
-  * @brief  Check if Timer 1 trigger interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG   LL_SYSCFG_IsActiveFlag_TIM1_TRG
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
-
-#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
-/**
-  * @brief  Check if Timer 1 commutation interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU   LL_SYSCFG_IsActiveFlag_TIM1_CCU
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
-
-#if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
-/**
-  * @brief  Check if Timer 1 capture compare interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC    LL_SYSCFG_IsActiveFlag_TIM1_CC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
-
-#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB)
-/**
-  * @brief  Check if Timer 2 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB   LL_SYSCFG_IsActiveFlag_TIM2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */
-
-#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
-/**
-  * @brief  Check if Timer 3 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB   LL_SYSCFG_IsActiveFlag_TIM3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
-
-#if defined(SYSCFG_ITLINE16_SR_TIM4_GLB)
-/**
-  * @brief  Check if Timer 3 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE16 SR_TIM4_GLB   LL_SYSCFG_IsActiveFlag_TIM4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM4(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM4_GLB) == (SYSCFG_ITLINE16_SR_TIM4_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE16_SR_TIM4_GLB */
-
-#if defined(SYSCFG_ITLINE17_SR_DAC)
-/**
-  * @brief  Check if DAC underrun interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE17 SR_DAC        LL_SYSCFG_IsActiveFlag_DAC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE17_SR_DAC */
-
-#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB)
-/**
-  * @brief  Check if Timer 6 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB   LL_SYSCFG_IsActiveFlag_TIM6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */
-
-#if defined(SYSCFG_ITLINE17_SR_LPTIM1_GLB)
-/**
-  * @brief  Check if LPTIM1 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE17 SR_LPTIM1_GLB   LL_SYSCFG_IsActiveFlag_LPTIM1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_LPTIM1_GLB) == (SYSCFG_ITLINE17_SR_LPTIM1_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE17_SR_LPTIM1_GLB */
-
-#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB)
-/**
-  * @brief  Check if Timer 7 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB   LL_SYSCFG_IsActiveFlag_TIM7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */
-
-#if defined(SYSCFG_ITLINE18_SR_LPTIM2_GLB)
-/**
-  * @brief  Check if LPTIM2 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE18 SR_LPTIM2_GLB   LL_SYSCFG_IsActiveFlag_LPTIM2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPTIM2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_LPTIM2_GLB) == (SYSCFG_ITLINE18_SR_LPTIM2_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE18_SR_LPTIM2_GLB */
-
-#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
-/**
-  * @brief  Check if Timer 14 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB  LL_SYSCFG_IsActiveFlag_TIM14
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
-
-#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB)
-/**
-  * @brief  Check if Timer 15 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB  LL_SYSCFG_IsActiveFlag_TIM15
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */
-
-#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
-/**
-  * @brief  Check if Timer 16 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB  LL_SYSCFG_IsActiveFlag_TIM16
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
-
-#if defined(SYSCFG_ITLINE21_SR_FDCAN1_IT0)
-/**
-  * @brief  Check if FDCAN1_IT0 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE21 SR_FDCAN1_IT0  LL_SYSCFG_IsActiveFlag_FDCAN1_IT0
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT0(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_FDCAN1_IT0) == (SYSCFG_ITLINE21_SR_FDCAN1_IT0)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE21_SR_FDCAN1_IT0 */
-#if defined(SYSCFG_ITLINE21_SR_FDCAN2_IT0)
-/**
-  * @brief  Check if FDCAN2_IT0 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE21 SR_FDCAN2_IT0  LL_SYSCFG_IsActiveFlag_FDCAN2_IT0
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN2_IT0(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_FDCAN2_IT0) == (SYSCFG_ITLINE21_SR_FDCAN2_IT0)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE21_SR_FDCAN2_IT0 */
-
-#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
-/**
-  * @brief  Check if Timer 17 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB  LL_SYSCFG_IsActiveFlag_TIM17
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
-
-#if defined(SYSCFG_ITLINE22_SR_FDCAN1_IT1)
-/**
-  * @brief  Check if FDCAN1_IT1 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE22 SR_FDCAN1_IT1  LL_SYSCFG_IsActiveFlag_FDCAN1_IT1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN1_IT1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_FDCAN1_IT1) == (SYSCFG_ITLINE22_SR_FDCAN1_IT1)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE22_SR_FDCAN1_IT1 */
-#if defined(SYSCFG_ITLINE22_SR_FDCAN2_IT1)
-/**
-  * @brief  Check if FDCAN2_IT1 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE22 SR_FDCAN2_IT1  LL_SYSCFG_IsActiveFlag_FDCAN2_IT1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FDCAN2_IT1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_FDCAN2_IT1) == (SYSCFG_ITLINE22_SR_FDCAN2_IT1)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE22_SR_FDCAN2_IT1 */
-
-#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
-/**
-  * @brief  Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
-  * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB   LL_SYSCFG_IsActiveFlag_I2C1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
-
-#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
-/**
-  * @brief  Check if I2C2 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB   LL_SYSCFG_IsActiveFlag_I2C2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
-
-#if defined(SYSCFG_ITLINE24_SR_I2C3_GLB)
-/**
-  * @brief  Check if I2C3 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE24 SR_I2C3_GLB   LL_SYSCFG_IsActiveFlag_I2C3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C3(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C3_GLB) == (SYSCFG_ITLINE24_SR_I2C3_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE24_SR_I2C3_GLB */
-
-#if defined(SYSCFG_ITLINE25_SR_SPI1)
-/**
-  * @brief  Check if SPI1 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE25 SR_SPI1       LL_SYSCFG_IsActiveFlag_SPI1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE25_SR_SPI1 */
-
-#if defined(SYSCFG_ITLINE26_SR_SPI2)
-/**
-  * @brief  Check if SPI2 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE26 SR_SPI2       LL_SYSCFG_IsActiveFlag_SPI2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE26_SR_SPI2 */
-
-#if defined(SYSCFG_ITLINE26_SR_SPI3)
-/**
-  * @brief  Check if SPI3 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE26 SR_SPI3       LL_SYSCFG_IsActiveFlag_SPI3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI3(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI3) == (SYSCFG_ITLINE26_SR_SPI3)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE26_SR_SPI3 */
-
-#if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
-/**
-  * @brief  Check if USART1 interrupt occurred or not, combined with EXTI line 25.
-  * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB  LL_SYSCFG_IsActiveFlag_USART1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
-
-#if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
-/**
-  * @brief  Check if USART2 interrupt occurred or not, combined with EXTI line 26.
-  * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB  LL_SYSCFG_IsActiveFlag_USART2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
-
-#if defined(SYSCFG_ITLINE28_SR_LPUART2_GLB)
-/**
-  * @brief  Check if LPUART2 interrupt occurred or not, combined with EXTI line 26.
-  * @rmtoll SYSCFG_ITLINE28 SR_LPUART2_GLB  LL_SYSCFG_IsActiveFlag_LPUART2
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART2(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_LPUART2_GLB) == (SYSCFG_ITLINE28_SR_LPUART2_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE28_SR_LPUART2_GLB */
-
-#if defined(SYSCFG_ITLINE29_SR_USART3_GLB)
-/**
-  * @brief  Check if USART3 interrupt occurred or not, combined with EXTI line 28.
-  * @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB  LL_SYSCFG_IsActiveFlag_USART3
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */
-
-#if defined(SYSCFG_ITLINE29_SR_USART4_GLB)
-/**
-  * @brief  Check if USART4 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB  LL_SYSCFG_IsActiveFlag_USART4
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */
-
-#if defined(SYSCFG_ITLINE29_SR_LPUART1_GLB)
-/**
-  * @brief  Check if LPUART1 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE29 SR_LPUART1_GLB  LL_SYSCFG_IsActiveFlag_LPUART1
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_LPUART1(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_LPUART1_GLB) == (SYSCFG_ITLINE29_SR_LPUART1_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE29_SR_LPUART1_GLB */
-
-#if defined(SYSCFG_ITLINE29_SR_USART5_GLB)
-/**
-  * @brief  Check if USART5 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB  LL_SYSCFG_IsActiveFlag_USART5
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */
-
-#if defined(SYSCFG_ITLINE29_SR_USART6_GLB)
-/**
-  * @brief  Check if USART6 interrupt occurred or not.
-  * @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB  LL_SYSCFG_IsActiveFlag_USART6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */
-
-#if defined(SYSCFG_ITLINE30_SR_CEC)
-/**
-  * @brief  Check if CEC interrupt occurred or not, combined with EXTI line 27.
-  * @rmtoll SYSCFG_ITLINE30 SR_CEC        LL_SYSCFG_IsActiveFlag_CEC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE30_SR_CEC */
-
-#if defined(SYSCFG_ITLINE31_SR_AES)
-/**
-  * @brief  Check if AES interrupt occurred or not
-  * @rmtoll SYSCFG_ITLINE31 SR_AES        LL_SYSCFG_IsActiveFlag_AES
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_AES(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_AES) == (SYSCFG_ITLINE31_SR_AES)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE31_SR_AES */
-
-#if defined(SYSCFG_ITLINE31_SR_RNG)
-/**
-  * @brief  Check if RNG interrupt occurred or not, combined with EXTI line 31.
-  * @rmtoll SYSCFG_ITLINE31 SR_RNG        LL_SYSCFG_IsActiveFlag_RNG
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RNG(void)
-{
-  return ((READ_BIT(SYSCFG->IT_LINE_SR[31], SYSCFG_ITLINE31_SR_RNG) == (SYSCFG_ITLINE31_SR_RNG)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_ITLINE31_SR_RNG */
-
-/**
-  * @brief  Set connections to TIM1/15/16/17 Break inputs
-  * @rmtoll SYSCFG_CFGR2 CLL   LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR2 SPL   LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR2 PVDL  LL_SYSCFG_SetTIMBreakInputs\n
-  *         SYSCFG_CFGR2 ECCL  LL_SYSCFG_GetTIMBreakInputs
-  * @param  Break This parameter can be a combination of the following values:
-  * @ifnot STM32G070xx
-  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
-  * @endif
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
-  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
-  *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
-{
-#if defined(SYSCFG_CFGR2_PVDL)
-  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
-#else
-  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_ECCL, Break);
-#endif /*SYSCFG_CFGR2_PVDL*/
-}
-
-/**
-  * @brief  Get connections to TIM1/15/16/17 Break inputs
-  * @rmtoll SYSCFG_CFGR2 CLL   LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR2 SPL   LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR2 PVDL  LL_SYSCFG_GetTIMBreakInputs\n
-  *         SYSCFG_CFGR2 ECCL  LL_SYSCFG_GetTIMBreakInputs
-  * @retval Returned value can be can be a combination of the following values:
-  * @ifnot STM32G070xx
-  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
-  * @endif
-  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
-  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
-  *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
-  *
-  *         (*) value not defined in all devices
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
-{
-#if defined(SYSCFG_CFGR2_PVDL)
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
-#else
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_ECCL));
-#endif /*SYSCFG_CFGR2_PVDL*/
-}
-
-/**
-  * @brief  Check if SRAM parity error detected
-  * @rmtoll SYSCFG_CFGR2 SPF      LL_SYSCFG_IsActiveFlag_SP
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
-{
-  return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear SRAM parity error flag
-  * @rmtoll SYSCFG_CFGR2 SPF      LL_SYSCFG_ClearFlag_SP
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
-{
-  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
-}
-
-#if defined(SYSCFG_CDEN_SUPPORT)
-/**
-  * @brief  Enable Clamping Diode on specific pin
-  * @rmtoll SYSCFG_CFGR2 PA1_CDEN   LL_SYSCFG_EnableClampingDiode\n
-  *         SYSCFG_CFGR2 PA3_CDEN   LL_SYSCFG_EnableClampingDiode\n
-  *         SYSCFG_CFGR2 PA5_CDEN   LL_SYSCFG_EnableClampingDiode\n
-  *         SYSCFG_CFGR2 PA6_CDEN   LL_SYSCFG_EnableClampingDiode\n
-  *         SYSCFG_CFGR2 PA13_CDEN  LL_SYSCFG_EnableClampingDiode\n
-  *         SYSCFG_CFGR2 PB0_CDEN   LL_SYSCFG_EnableClampingDiode\n
-  *         SYSCFG_CFGR2 PB1_CDEN   LL_SYSCFG_EnableClampingDiode\n
-  *         SYSCFG_CFGR1 PB2_CDEN   LL_SYSCFG_EnableClampingDiode
-  * @param  ConfigClampingDiode This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableClampingDiode(uint32_t ConfigClampingDiode)
-{
-  SET_BIT(SYSCFG->CFGR2, ConfigClampingDiode);
-}
-
-/**
-  * @brief  Disable Clamping Diode on specific pin
-  * @rmtoll SYSCFG_CFGR2 PA1_CDEN   LL_SYSCFG_DisableClampingDiode\n
-  *         SYSCFG_CFGR2 PA3_CDEN   LL_SYSCFG_DisableClampingDiode\n
-  *         SYSCFG_CFGR2 PA5_CDEN   LL_SYSCFG_DisableClampingDiode\n
-  *         SYSCFG_CFGR2 PA6_CDEN   LL_SYSCFG_DisableClampingDiode\n
-  *         SYSCFG_CFGR2 PA13_CDEN  LL_SYSCFG_DisableClampingDiode\n
-  *         SYSCFG_CFGR2 PB0_CDEN   LL_SYSCFG_DisableClampingDiode\n
-  *         SYSCFG_CFGR2 PB1_CDEN   LL_SYSCFG_DisableClampingDiode\n
-  *         SYSCFG_CFGR1 PB2_CDEN   LL_SYSCFG_DisableClampingDiode
-  * @param  ConfigClampingDiode This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableClampingDiode(uint32_t ConfigClampingDiode)
-{
-  CLEAR_BIT(SYSCFG->CFGR2, ConfigClampingDiode);
-}
-/**
-  * @brief  Indicates whether clamping diode(s) is(are) enabled.
-  * @rmtoll SYSCFG_CFGR2 PA1_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
-  *         SYSCFG_CFGR2 PA3_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
-  *         SYSCFG_CFGR2 PA5_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
-  *         SYSCFG_CFGR2 PA6_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
-  *         SYSCFG_CFGR2 PA13_CDEN  LL_SYSCFG_IsEnabledClampingDiode\n
-  *         SYSCFG_CFGR2 PB0_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
-  *         SYSCFG_CFGR2 PB1_CDEN   LL_SYSCFG_IsEnabledClampingDiode\n
-  *         SYSCFG_CFGR1 PB2_CDEN   LL_SYSCFG_IsEnabledClampingDiode
-  * @param  ConfigClampingDiode This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_CFGR2_PA1_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA3_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA5_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA6_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PA13_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PB0_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PB1_CDEN
-  *         @arg @ref LL_SYSCFG_CFGR2_PB2_CDEN
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledClampingDiode(uint32_t ConfigClampingDiode)
-{
-  return ((READ_BIT(SYSCFG->CFGR2, ConfigClampingDiode) == (ConfigClampingDiode)) ? 1UL : 0UL);
-}
-#endif /* SYSCFG_CDEN_SUPPORT */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
-  * @{
-  */
-
-/**
-  * @brief  Return the device identifier
-  * @note For STM32G081xx devices, the device ID is 0x460
-  * @rmtoll DBG_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
-  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
-{
-  return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_DEV_ID));
-}
-
-/**
-  * @brief  Return the device revision identifier
-  * @note This field indicates the revision of the device.
-  * @rmtoll DBG_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
-  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
-{
-  return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_REV_ID) >> DBG_IDCODE_REV_ID_Pos);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP mode
-  * @rmtoll DBG_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBG->CR, DBG_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP mode
-  * @rmtoll DBG_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode
-  * @rmtoll DBG_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode
-  * @rmtoll DBG_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Freeze APB1 peripherals (group1 peripherals)
-  * @rmtoll DBG_APB_FZ1 DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_I2C1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_I2C2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_LPTIM2_STOP         LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ1 DBG_LPTIM1_STOP         LL_DBGMCU_APB1_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBG->APBFZ1, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
-  * @rmtoll DBG_APB_FZ1 DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_LPTIM2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ1 DBG_LPTIM1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP (*)
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBG->APBFZ1, Periphs);
-}
-
-/**
-  * @brief  Freeze APB2 peripherals
-  * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ2 DBG_TIM14_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ2 DBG_TIM15_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ2 DBG_TIM16_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBG_APB_FZ2 DBG_TIM17_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM14_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBG->APBFZ2, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB2 peripherals
-  * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ2 DBG_TIM14_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ2 DBG_TIM15_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ2 DBG_TIM16_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         DBG_APB_FZ2 DBG_TIM17_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM14_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
-  *
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBG->APBFZ2, Periphs);
-}
-/**
-  * @}
-  */
-
-#if defined(VREFBUF)
-/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
-  * @{
-  */
-
-/**
-  * @brief  Enable Internal voltage reference
-  * @rmtoll VREFBUF_CSR  VREFBUF_CSR_ENVR          LL_VREFBUF_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_VREFBUF_Enable(void)
-{
-  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-}
-
-/**
-  * @brief  Disable Internal voltage reference
-  * @rmtoll VREFBUF_CSR  VREFBUF_CSR_ENVR          LL_VREFBUF_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_VREFBUF_Disable(void)
-{
-  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
-}
-
-/**
-  * @brief  Enable high impedance (VREF+pin is high impedance)
-  * @rmtoll VREFBUF_CSR  VREFBUF_CSR_HIZ           LL_VREFBUF_EnableHIZ
-  * @retval None
-  */
-__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
-{
-  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
-}
-
-/**
-  * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
-  * @rmtoll VREFBUF_CSR  VREFBUF_CSR_HIZ           LL_VREFBUF_DisableHIZ
-  * @retval None
-  */
-__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
-{
-  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
-}
-
-/**
-  * @brief  Set the Voltage reference scale
-  * @rmtoll VREFBUF_CSR  VREFBUF_CSR_VRS           LL_VREFBUF_SetVoltageScaling
-  * @param  Scale This parameter can be one of the following values:
-  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
-  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
-  * @retval None
-  */
-__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
-{
-  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
-}
-
-/**
-  * @brief  Get the Voltage reference scale
-  * @rmtoll VREFBUF_CSR  VREFBUF_CSR_VRS           LL_VREFBUF_GetVoltageScaling
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
-  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
-  */
-__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
-{
-  return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
-}
-
-/**
-  * @brief  Check if Voltage reference buffer is ready
-  * @rmtoll VREFBUF_CSR  VREFBUF_CSR_VRS           LL_VREFBUF_IsVREFReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
-{
-  return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the trimming code for VREFBUF calibration
-  * @rmtoll VREFBUF_CCR  VREFBUF_CCR_TRIM          LL_VREFBUF_GetTrimming
-  * @retval Between 0 and 0x3F
-  */
-__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
-{
-  return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
-}
-
-/**
-  * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
-  * @note   VrefBuf voltage scale is calibrated in production for each device,
-  *         using voltage scale 1. This calibration value is loaded
-  *         as default trimming value at device power up.
-  *         This trimming value can be fine tuned for voltage scales 0 and 1
-  *         using this function.
-  * @rmtoll VREFBUF_CCR  VREFBUF_CCR_TRIM          LL_VREFBUF_SetTrimming
-  * @param  Value Between 0 and 0x3F
-  * @retval None
-  */
-__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
-{
-  WRITE_REG(VREFBUF->CCR, Value);
-}
-
-/**
-  * @}
-  */
-#endif /* VREFBUF */
-
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
-  * @{
-  */
-
-/**
-  * @brief  Set FLASH Latency
-  * @rmtoll FLASH_ACR    FLASH_ACR_LATENCY       LL_FLASH_SetLatency
-  * @param  Latency This parameter can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  *         @arg @ref LL_FLASH_LATENCY_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
-  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
-  * @brief  Get FLASH Latency
-  * @rmtoll FLASH_ACR    FLASH_ACR_LATENCY       LL_FLASH_GetLatency
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  *         @arg @ref LL_FLASH_LATENCY_2
-  */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
-{
-  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
-  * @brief  Enable Prefetch
-  * @rmtoll FLASH_ACR    FLASH_ACR_PRFTEN        LL_FLASH_EnablePrefetch
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
-  * @brief  Disable Prefetch
-  * @rmtoll FLASH_ACR    FLASH_ACR_PRFTEN        LL_FLASH_DisablePrefetch
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
-  * @brief  Check if Prefetch buffer is enabled
-  * @rmtoll FLASH_ACR    FLASH_ACR_PRFTEN        LL_FLASH_IsPrefetchEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
-{
-  return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Instruction cache
-  * @rmtoll FLASH_ACR    FLASH_ACR_ICEN          LL_FLASH_EnableInstCache
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
-}
-
-/**
-  * @brief  Disable Instruction cache
-  * @rmtoll FLASH_ACR    FLASH_ACR_ICEN          LL_FLASH_DisableInstCache
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
-}
-
-/**
-  * @brief  Enable Instruction cache reset
-  * @note  bit can be written only when the instruction cache is disabled
-  * @rmtoll FLASH_ACR    FLASH_ACR_ICRST         LL_FLASH_EnableInstCacheReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
-}
-
-/**
-  * @brief  Disable Instruction cache reset
-  * @rmtoll FLASH_ACR    FLASH_ACR_ICRST         LL_FLASH_DisableInstCacheReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBG) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_SYSTEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_tim.h

@@ -1,5277 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_tim.h
-  * @author  MCD Application Team
-  * @brief   Header file of TIM LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32G0xx_LL_TIM_H
-#define __STM32G0xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) ||  defined (TIM14) ||  defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
-
-/** @defgroup TIM_LL TIM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
-  * @{
-  */
-static const uint8_t OFFSET_TAB_CCMRx[] =
-{
-  0x00U,   /* 0: TIMx_CH1  */
-  0x00U,   /* 1: TIMx_CH1N */
-  0x00U,   /* 2: TIMx_CH2  */
-  0x00U,   /* 3: TIMx_CH2N */
-  0x04U,   /* 4: TIMx_CH3  */
-  0x04U,   /* 5: TIMx_CH3N */
-  0x04U,   /* 6: TIMx_CH4  */
-  0x3CU,   /* 7: TIMx_CH5  */
-  0x3CU    /* 8: TIMx_CH6  */
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] =
-{
-  0U,            /* 0: OC1M, OC1FE, OC1PE */
-  0U,            /* 1: - NA */
-  8U,            /* 2: OC2M, OC2FE, OC2PE */
-  0U,            /* 3: - NA */
-  0U,            /* 4: OC3M, OC3FE, OC3PE */
-  0U,            /* 5: - NA */
-  8U,            /* 6: OC4M, OC4FE, OC4PE */
-  0U,            /* 7: OC5M, OC5FE, OC5PE */
-  8U             /* 8: OC6M, OC6FE, OC6PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] =
-{
-  0U,            /* 0: CC1S, IC1PSC, IC1F */
-  0U,            /* 1: - NA */
-  8U,            /* 2: CC2S, IC2PSC, IC2F */
-  0U,            /* 3: - NA */
-  0U,            /* 4: CC3S, IC3PSC, IC3F */
-  0U,            /* 5: - NA */
-  8U,            /* 6: CC4S, IC4PSC, IC4F */
-  0U,            /* 7: - NA */
-  0U             /* 8: - NA */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] =
-{
-  0U,            /* 0: CC1P */
-  2U,            /* 1: CC1NP */
-  4U,            /* 2: CC2P */
-  6U,            /* 3: CC2NP */
-  8U,            /* 4: CC3P */
-  10U,           /* 5: CC3NP */
-  12U,           /* 6: CC4P */
-  16U,           /* 7: CC5P */
-  20U            /* 8: CC6P */
-};
-
-static const uint8_t SHIFT_TAB_OISx[] =
-{
-  0U,            /* 0: OIS1 */
-  1U,            /* 1: OIS1N */
-  2U,            /* 2: OIS2 */
-  3U,            /* 3: OIS2N */
-  4U,            /* 4: OIS3 */
-  5U,            /* 5: OIS3N */
-  6U,            /* 6: OIS4 */
-  8U,            /* 7: OIS5 */
-  10U            /* 8: OIS6 */
-};
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
-  * @{
-  */
-
-/* Defines used for the bit position in the register and perform offsets */
-#if defined(COMP3)
-#define TIM_POSITION_BRK_SOURCE \
-  ((Source == LL_TIM_BKIN_SOURCE_BKIN)    ? 0U :\
-   (Source == LL_TIM_BKIN_SOURCE_BKCOMP1) ? 1U :\
-   (Source == LL_TIM_BKIN_SOURCE_BKCOMP2) ? 2U :3U)
-#else
-#define TIM_POSITION_BRK_SOURCE            ((Source >> 1U) & 0x1FUL)
-#endif
-
-/* Generic bit definitions for TIMx_AF1 register */
-#define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
-#define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
-
-
-/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7F)
-#define DT_DELAY_2 ((uint8_t)0x3F)
-#define DT_DELAY_3 ((uint8_t)0x1F)
-#define DT_DELAY_4 ((uint8_t)0x1F)
-
-/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00)
-#define DT_RANGE_2 ((uint8_t)0x80)
-#define DT_RANGE_3 ((uint8_t)0xC0)
-#define DT_RANGE_4 ((uint8_t)0xE0)
-
-/** Legacy definitions for compatibility purpose
-@cond 0
-  */
-/**
-@endcond
-  */
-
-#define OCREF_CLEAR_SELECT_Pos (16U)
-#define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos)                /*!< 0x00010000 */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
-  * @{
-  */
-/** @brief  Convert channel id into channel index.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval none
-  */
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
-   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
-
-/** @brief  Calculate the deadtime sampling period(in ps).
-  * @param  __TIMCLK__ timer input clock frequency (in Hz).
-  * @param  __CKD__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @retval none
-  */
-#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
-  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
-   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
-   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
-/**
-  * @}
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
-  * @{
-  */
-
-/**
-  * @brief  TIM Time Base configuration structure definition.
-  */
-typedef struct
-{
-  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetPrescaler().*/
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetCounterMode().*/
-
-  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-                                   Some timer instances may support 32 bits counters. In that case this parameter must
-                                   be a number between 0x0000 and 0xFFFFFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetAutoReload().*/
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetClockDivision().*/
-
-  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
-                                   reaches zero, an update event is generated and counting restarts
-                                   from the RCR value (N).
-                                   This means in PWM mode that (N+1) corresponds to:
-                                      - the number of PWM periods in edge-aligned mode
-                                      - the number of half PWM period in center-aligned mode
-                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
-                                   Max_Data = 0xFF.
-                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
-                                   Max_Data = 0xFFFF.
-
-                                   This feature can be modified afterwards using unitary function
-                                   @ref LL_TIM_SetRepetitionCounter().*/
-} LL_TIM_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the output mode.
-                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetMode().*/
-
-  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
-                               This feature can be modified afterwards using unitary functions
-                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
-  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
-                               This feature can be modified afterwards using unitary functions
-                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
-  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
-                               This feature can be modified afterwards using unitary function
-                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetPolarity().*/
-
-  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
-                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetPolarity().*/
-
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetIdleState().*/
-
-  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_OC_SetIdleState().*/
-} LL_TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM Input Capture configuration structure definition.
-  */
-
-typedef struct
-{
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t ICActiveInput; /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                               This feature can be modified afterwards using unitary function
-                               @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-
-/**
-  * @brief  TIM Encoder interface configuration structure definition.
-  */
-typedef struct
-{
-  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
-                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_SetEncoderMode().*/
-
-  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
-                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetActiveInput().*/
-
-  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
-                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
-                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
-                                 This feature can be modified afterwards using unitary function
-                                 @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-/**
-  * @brief  TIM Hall sensor interface configuration structure definition.
-  */
-typedef struct
-{
-
-  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
-                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_IC_SetPolarity().*/
-
-  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
-                                    Prescaler must be set to get a maximum counter period longer than the
-                                    time interval between 2 consecutive changes on the Hall inputs.
-                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_IC_SetPrescaler().*/
-
-  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
-                                    This parameter can be a value of
-                                    @ref TIM_LL_EC_IC_FILTER.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_IC_SetFilter().*/
-
-  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
-                                    A positive pulse (TRGO event) is generated with a programmable delay every time
-                                    a change occurs on the Hall inputs.
-                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
-
-                                    This feature can be modified afterwards using unitary function
-                                    @ref LL_TIM_OC_SetCompareCH2().*/
-} LL_TIM_HALLSENSOR_InitTypeDef;
-
-/**
-  * @brief  BDTR (Break and Dead Time) structure definition
-  */
-typedef struct
-{
-  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
-                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_SetOffStates()
-
-                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
-                                       programmed. */
-
-  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
-                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_SetOffStates()
-
-                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
-                                      programmed. */
-
-  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
-                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
-
-                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
-                                      register has been written, their content is frozen until the next reset.*/
-
-  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
-                                      switching-on of the outputs.
-                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_OC_SetDeadTime()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
-                                       programmed. */
-
-  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_ConfigBRK()
-
-                                      @note Bidirectional break input is only supported by advanced timers instances.
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK2()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
-
-                                      This feature can be modified afterwards using unitary function
-                                      @ref LL_TIM_ConfigBRK2()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
-                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_ConfigBRK2()
-
-                                      @note Bidirectional break input is only supported by advanced timers instances.
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-
-  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
-                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
-
-                                      This feature can be modified afterwards using unitary functions
-                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
-
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been
-                                      programmed. */
-} LL_TIM_BDTR_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
-  * @{
-  */
-#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
-#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
-#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
-#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
-#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
-#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
-#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
-#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
-#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
-#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
-#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
-#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
-  * @{
-  */
-#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
-#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
-  * @{
-  */
-#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
-#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
-  * @{
-  */
-#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
-#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
-  * @{
-  */
-#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
-#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
-#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
-  * @{
-  */
-#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
-  * @{
-  */
-#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
-  * @{
-  */
-#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
-  * @{
-  */
-#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
-  * @{
-  */
-#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
-  * @{
-  */
-#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
-#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
-  * @{
-  */
-#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
-  * @{
-  */
-#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
-#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
-#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
-#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CHANNEL Channel
-  * @{
-  */
-#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
-#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
-#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
-#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
-#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
-#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
-#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
-#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
-#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
-  * @{
-  */
-#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
-#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
-  * @{
-  */
-#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
-#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
-#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
-#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
-#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
-#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
-#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
-#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
-#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
-#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
-#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
-  * @{
-  */
-#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
-#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
-  * @{
-  */
-#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
-#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
-  * @{
-  */
-#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
-#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
-#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
-  * @{
-  */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
-  * @{
-  */
-#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
-#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
-  * @{
-  */
-#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
-  * @{
-  */
-#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
-#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
-#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
-  * @{
-  */
-#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
-  * @{
-  */
-#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TRGO Trigger Output
-  * @{
-  */
-#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
-#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
-#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
-#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
-#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
-  * @{
-  */
-#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
-#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
-#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
-#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
-#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
-  * @{
-  */
-#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
-#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
-#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
-#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
-#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TS Trigger Selection
-  * @{
-  */
-#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
-#if defined(USB_BASE)
-#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
-#endif /* USB_BASE */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
-  * @{
-  */
-#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
-#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
-  * @{
-  */
-#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
-#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
-#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
-#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
-  * @{
-  */
-#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
-  * @{
-  */
-#define LL_TIM_ETRSOURCE_GPIO                  0x00000000U                                                 /*!< ETR input is connected to GPIO */
-#if defined(COMP1) && defined(COMP2)
-#define LL_TIM_ETRSOURCE_COMP1                 TIM1_AF1_ETRSEL_0                                 /*!< ETR input is connected to COMP1_OUT */
-#define LL_TIM_ETRSOURCE_COMP2                 TIM1_AF1_ETRSEL_1                                 /*!< ETR input is connected to COMP2_OUT */
-#endif /* COMP1 && COMP2 */
-#if defined(COMP3)
-#define LL_TIM_ETRSOURCE_COMP3                 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP3_OUT */
-#endif /* COMP3 */
-#define LL_TIM_ETRSOURCE_ADC1_AWD1             (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
-#define LL_TIM_ETRSOURCE_ADC1_AWD2             TIM1_AF1_ETRSEL_2                                 /*!< ETR input is connected to ADC1 analog watchdog 2 */
-#define LL_TIM_ETRSOURCE_ADC1_AWD3             (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
-#define LL_TIM_ETRSOURCE_LSE                   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
-#define LL_TIM_ETRSOURCE_MCO                   TIM1_AF1_ETRSEL_2                                 /*!< ETR input is connected to MCO */
-#define LL_TIM_ETRSOURCE_MCO2                  (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MCO2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
-  * @{
-  */
-#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
-#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
-  * @{
-  */
-#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
-#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
-  * @{
-  */
-#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
-#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
-  * @{
-  */
-#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OSSI OSSI
-  * @{
-  */
-#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OSSR OSSR
-  * @{
-  */
-#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
-  * @{
-  */
-#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
-#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
-  * @{
-  */
-#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
-#if defined(COMP1) && defined(COMP2)
-#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
-#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
-#endif /* COMP1 && COMP2 */
-#if defined(COMP3)
-#define LL_TIM_BKIN_SOURCE_BKCOMP3             TIM1_AF1_BKCMP3E    /*!< internal signal: COMP3 output */
-#endif /* COMP3 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
-  * @{
-  */
-#define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
-#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
-  * @{
-  */
-#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
-#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
-  * @{
-  */
-#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
-#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
-  * @{
-  */
-#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_OR1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_OR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
-  * @{
-  */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM1_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM1 input 1 is connected to GPIO */
-#if defined(COMP1)
-#define LL_TIM_TIM1_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM1 input 1 is connected to COMP1_OUT */
-#endif /* COMP1 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM1_TI2_RMP  TIM1 Timer Input Ch2 Remap
-  * @{
-  */
-#define LL_TIM_TIM1_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM1 input 2 is connected to GPIO */
-#if defined(COMP2)
-#define LL_TIM_TIM1_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_0                                /*!< TIM1 input 2 is connected to COMP2_OUT */
-#endif /* COMP2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM1_TI3_RMP  TIM1 Timer Input Ch3 Remap
-  * @{
-  */
-#define LL_TIM_TIM1_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM1 input 3 is connected to GPIO */
-#if defined(COMP3)
-#define LL_TIM_TIM1_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM1 input 3 is connected to COMP3_OUT */
-#endif /* COMP3 */
-/**
-  * @}
-  */
-
-#if defined(TIM2)
-/** @defgroup TIM_LL_EC_TIM2_TI1_RMP  TIM2 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM2_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 1 is connected to GPIO */
-#define LL_TIM_TIM2_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM2 input 1 is connected to COMP1_OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM2_TI2_RMP  TIM2 Timer Input Ch2 Remap
-  * @{
-  */
-#define LL_TIM_TIM2_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 2 is connected to GPIO */
-#define LL_TIM_TIM2_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_0                                /*!< TIM2 input 2 is connected to COMP2_OUT */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM2_TI3_RMP  TIM2 Timer Input Ch3 Remap
-  * @{
-  */
-#define LL_TIM_TIM2_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM2 input 3 is connected to GPIO */
-#if defined(COMP3)
-#define LL_TIM_TIM2_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM2 input 3 is connected to COMP3_OUT */
-#endif /* COMP3 */
-/**
-  * @}
-  */
-#endif /* TIM2 */
-
-/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM3_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 1 is connected to GPIO */
-#if defined(COMP1)
-#define LL_TIM_TIM3_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM3 input 1 is connected to COMP1_OUT */
-#endif /* COMP1 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM3_TI2_RMP  TIM3 Timer Input Ch2 Remap
-  * @{
-  */
-#define LL_TIM_TIM3_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 2 is connected to GPIO */
-#if defined(COMP2)
-#define LL_TIM_TIM3_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_0                                /*!< TIM3 input 2 is connected to COMP2_OUT */
-#endif /* COMP2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM3_TI3_RMP  TIM3 Timer Input Ch3 Remap
-  * @{
-  */
-#define LL_TIM_TIM3_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM3 input 3 is connected to GPIO */
-#if defined(COMP3)
-#define LL_TIM_TIM3_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM3 input 3 is connected to COMP3_OUT */
-#endif /* COMP3 */
-/**
-  * @}
-  */
-
-#if defined(TIM4)
-/** @defgroup TIM_LL_EC_TIM4_TI1_RMP  TIM4 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM4_TI1_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 1 is connected to GPIO */
-#if defined(COMP1)
-#define LL_TIM_TIM4_TI1_RMP_COMP1  TIM_TISEL_TI1SEL_0                                /*!< TIM4 input 1 is connected to COMP1_OUT */
-#endif /* COMP1 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM4_TI2_RMP  TIM4 Timer Input Ch2 Remap
-  * @{
-  */
-#define LL_TIM_TIM4_TI2_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 2 is connected to GPIO */
-#if defined(COMP2)
-#define LL_TIM_TIM4_TI2_RMP_COMP2  TIM_TISEL_TI2SEL_0                                /*!< TIM4 input 2 is connected to COMP2_OUT */
-#endif /* COMP2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM4_TI3_RMP  TIM4 Timer Input Ch3 Remap
-  * @{
-  */
-#define LL_TIM_TIM4_TI3_RMP_GPIO   0x00000000U                                       /*!< TIM4 input 3 is connected to GPIO */
-#if defined(COMP3)
-#define LL_TIM_TIM4_TI3_RMP_COMP3  TIM_TISEL_TI3SEL_0                                /*!< TIM4 input 3 is connected to COMP3_OUT */
-#endif /* COMP3 */
-/**
-  * @}
-  */
-#endif /* TIM4 */
-
-/** @defgroup TIM_LL_EC_TIM14_TI1_RMP  TIM14 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM14_TI1_RMP_GPIO     0x00000000U                                    /*!< TIM14 input 1 is connected to GPIO */
-#define LL_TIM_TIM14_TI1_RMP_RTC_CLK  TIM_TISEL_TI1SEL_0                             /*!< TIM14 input 1 is connected to RTC clock */
-#define LL_TIM_TIM14_TI1_RMP_HSE_32   TIM_TISEL_TI1SEL_1                             /*!< TIM14 input 1 is connected to HSE/32 clock */
-#define LL_TIM_TIM14_TI1_RMP_MCO     (TIM_TISEL_TI1SEL_0  | TIM_TISEL_TI1SEL_1)     /*!< TIM14 input 1 is connected to MCO */
-#define LL_TIM_TIM14_TI1_RMP_MCO2    TIM_TISEL_TI1SEL_2                             /*!< TIM14 input 1 is connected to MCO2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
-  * @{
-  */
-#if defined(TIM15)
-#define LL_TIM_TIM15_TI1_RMP_GPIO     0x00000000U                                    /*!< TIM15 input 1 is connected to GPIO */
-#if defined(TIM2)
-#define LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0                             /*!< TIM15 input 1 is connected to TIM2 input 1 */
-#endif /* TIM2 */
-#if defined(TIM3)
-#define LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1                             /*!< TIM15 input 1 is connected to TIM3 input 1 */
-#endif /* TIM3 */
-#endif /* TIM15 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
-  * @{
-  */
-#if defined(TIM15)
-#define LL_TIM_TIM15_TI2_RMP_GPIO     0x00000000U                                    /*!< TIM15 input 2 is connected to GPIO */
-#if defined(TIM2)
-#define LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0                             /*!< TIM15 input 2 is connected to TIM2 input 2 */
-#endif /* TIM2 */
-#if defined(TIM3)
-#define LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1                             /*!< TIM15 input 2 is connected to TIM3 input 2 */
-#endif /* TIM3 */
-#endif /* TIM15 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM16_TI1_RMP_GPIO    0x00000000U                                     /*!< TIM16 input 1 is connected to GPIO */
-#define LL_TIM_TIM16_TI1_RMP_LSI     TIM_TISEL_TI1SEL_0                              /*!< TIM16 input 1 is connected to LSI */
-#define LL_TIM_TIM16_TI1_RMP_LSE     TIM_TISEL_TI1SEL_1                              /*!< TIM16 input 1 is connected to LSE */
-#define LL_TIM_TIM16_TI1_RMP_RTC_WK  (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)       /*!< TIM16 input 1 is connected to RTC_WAKEUP */
-#define LL_TIM_TIM16_TI1_RMP_MCO2    TIM_TISEL_TI1SEL_2                              /*!< TIM16 input 1 is connected to MCO2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
-  * @{
-  */
-#define LL_TIM_TIM17_TI1_RMP_GPIO    0x00000000U                                     /*!< TIM17 input 1 is connected to GPIO */
-#define LL_TIM_TIM17_TI1_RMP_HSI48   TIM_TISEL_TI1SEL_0                              /*!< TIM17 input 1 is connected to HSI48/256 */
-#define LL_TIM_TIM17_TI1_RMP_HSE_32  TIM_TISEL_TI1SEL_1                              /*!< TIM17 input 1 is connected to HSE/32 clock */
-#define LL_TIM_TIM17_TI1_RMP_MCO    (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1)        /*!< TIM17 input 1 is connected to MCO */
-#define LL_TIM_TIM17_TI1_RMP_MCO2    TIM_TISEL_TI1SEL_2                              /*!< TIM17 input 1 is connected to MCO2 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
-  * @{
-  */
-#define LL_TIM_OCREF_CLR_INT_ETR         OCREF_CLEAR_SELECT_Msk       /*!< OCREF_CLR_INT is connected to ETRF */
-#if defined(COMP1) && defined(COMP2)
-#define LL_TIM_OCREF_CLR_INT_COMP1       0x00000000U                  /*!< OCREF clear input is connected to COMP1_OUT */
-#if defined(COMP3)
-#define LL_TIM_OCREF_CLR_INT_COMP2       TIM1_OR1_OCREF_CLR_0         /*!< OCREF clear input is connected to COMP2_OUT */
-#define LL_TIM_OCREF_CLR_INT_COMP3       TIM1_OR1_OCREF_CLR_1         /*!< OCREF clear input is connected to COMP3_OUT */
-#else
-#define LL_TIM_OCREF_CLR_INT_COMP2       TIM1_OR1_OCREF_CLR           /*!< OCREF clear input is connected to COMP2_OUT */
-#endif /* COMP3 */
-#endif /* COMP1 & COMP2 */
-/**
-  * @}
-  */
-
-/** Legacy definitions for compatibility purpose
-@cond 0
-  */
-#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
-/**
-@endcond
-  */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-/**
-  * @brief  Write a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in TIM register.
-  * @param  __INSTANCE__ TIM Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
-  * @{
-  */
-
-/**
-  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
-  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
-  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
-  *        to TIMx_CNT register bit 31)
-  * @param  __CNT__ Counter value
-  * @retval UIF status bit
-  */
-#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
-  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
-
-/**
-  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
-  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __CKD__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @param  __DT__ deadtime duration (in ns)
-  * @retval DTG[0:7]
-  */
-#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
-  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
-    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
-    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
-    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
-                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
-    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
-    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
-                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
-    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
-    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
-                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
-    0U)
-
-/**
-  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
-  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __CNTCLK__ counter clock frequency (in Hz)
-  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
-  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
-  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __FREQ__ output signal frequency (in Hz)
-  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
-  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
-
-/**
-  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
-  *         active/inactive delay.
-  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
-  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
-              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
-  *         (when the timer operates in one pulse mode).
-  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
-  * @param  __TIMCLK__ timer input clock frequency (in Hz)
-  * @param  __PSC__ prescaler
-  * @param  __DELAY__ timer output compare active/inactive delay (in us)
-  * @param  __PULSE__ pulse duration (in us)
-  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
-  */
-#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
-  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
-              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
-
-/**
-  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
-  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
-  * @param  __ICPSC__ This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
-  */
-#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
-  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
-  * @{
-  */
-/**
-  * @brief  Enable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Disable timer counter.
-  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
-  * @brief  Indicates whether the timer counter is enabled.
-  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Disable update event generation.
-  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
-  * @brief  Indicates whether update event generation is enabled.
-  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
-  * @param  TIMx Timer instance
-  * @retval Inverted state of bit (0 or 1).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set update event source
-  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
-  *       generate an update interrupt or DMA request if enabled:
-  *        - Counter overflow/underflow
-  *        - Setting the UG bit
-  *        - Update generation through the slave mode controller
-  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
-  *       overflow/underflow generates an update interrupt or DMA request if enabled.
-  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
-  * @param  TIMx Timer instance
-  * @param  UpdateSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
-}
-
-/**
-  * @brief  Get actual event update source
-  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
-  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
-}
-
-/**
-  * @brief  Set one pulse mode (one shot v.s. repetitive).
-  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
-  * @param  TIMx Timer instance
-  * @param  OnePulseMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
-}
-
-/**
-  * @brief  Get actual one pulse mode.
-  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
-  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
-}
-
-/**
-  * @brief  Set the timer counter counting mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
-  *       requires a timer reset to avoid unexpected direction
-  *       due to DIR bit readonly in center aligned mode.
-  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
-  *         CR1          CMS           LL_TIM_SetCounterMode
-  * @param  TIMx Timer instance
-  * @param  CounterMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
-{
-  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
-}
-
-/**
-  * @brief  Get actual counter mode.
-  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
-  *       check whether or not the counter mode selection feature is supported
-  *       by a timer instance.
-  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
-  *         CR1          CMS           LL_TIM_GetCounterMode
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERMODE_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
-  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
-{
-  uint32_t counter_mode;
-
-  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
-
-  if (counter_mode == 0U)
-  {
-    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-  }
-
-  return counter_mode;
-}
-
-/**
-  * @brief  Enable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Disable auto-reload (ARR) preload.
-  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
-  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
-  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
-  *         (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
-  * @param  TIMx Timer instance
-  * @param  ClockDivision This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
-{
-  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
-}
-
-/**
-  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
-  *         generators (when supported) and the digital filters.
-  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
-  *       whether or not the clock division feature is supported by the timer
-  *       instance.
-  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
-  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
-}
-
-/**
-  * @brief  Set the counter value.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @rmtoll CNT          CNT           LL_TIM_SetCounter
-  * @param  TIMx Timer instance
-  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
-{
-  WRITE_REG(TIMx->CNT, Counter);
-}
-
-/**
-  * @brief  Get the counter value.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @rmtoll CNT          CNT           LL_TIM_GetCounter
-  * @param  TIMx Timer instance
-  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CNT));
-}
-
-/**
-  * @brief  Get the current direction of the counter
-  * @rmtoll CR1          DIR           LL_TIM_GetDirection
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
-  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-}
-
-/**
-  * @brief  Set the prescaler value.
-  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
-  * @note The prescaler can be changed on the fly as this control register is buffered. The new
-  *       prescaler ratio is taken into account at the next update event.
-  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
-  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Prescaler between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
-{
-  WRITE_REG(TIMx->PSC, Prescaler);
-}
-
-/**
-  * @brief  Get the prescaler value.
-  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
-  * @param  TIMx Timer instance
-  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->PSC));
-}
-
-/**
-  * @brief  Set the auto-reload value.
-  * @note The counter is blocked while the auto-reload value is null.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
-  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
-  * @param  TIMx Timer instance
-  * @param  AutoReload between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
-{
-  WRITE_REG(TIMx->ARR, AutoReload);
-}
-
-/**
-  * @brief  Get the auto-reload value.
-  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @param  TIMx Timer instance
-  * @retval Auto-reload value
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->ARR));
-}
-
-/**
-  * @brief  Set the repetition counter value.
-  * @note For advanced timer instances RepetitionCounter can be up to 65535.
-  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a repetition counter.
-  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
-  * @param  TIMx Timer instance
-  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
-{
-  WRITE_REG(TIMx->RCR, RepetitionCounter);
-}
-
-/**
-  * @brief  Get the repetition counter value.
-  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a repetition counter.
-  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
-  * @param  TIMx Timer instance
-  * @retval Repetition counter value
-  */
-__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->RCR));
-}
-
-/**
-  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
-  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
-  *       in an atomic way.
-  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
-}
-
-/**
-  * @brief  Disable update interrupt flag (UIF) remapping.
-  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
-}
-
-/**
-  * @brief  Indicate whether update interrupt flag (UIF) copy is set.
-  * @param  Counter Counter value
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
-{
-  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
-  * @{
-  */
-/**
-  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
-  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
-  *       they are updated only when a commutation event (COM) occurs.
-  * @note Only on channels that have a complementary output.
-  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance is able to generate a commutation event.
-  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
-  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
-  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance is able to generate a commutation event.
-  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
-  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
-  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance is able to generate a commutation event.
-  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
-  * @param  TIMx Timer instance
-  * @param  CCUpdateSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
-  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
-}
-
-/**
-  * @brief  Set the trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @param  DMAReqTrigger This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
-}
-
-/**
-  * @brief  Get actual trigger of the capture/compare DMA request.
-  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
-  * @param  TIMx Timer instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
-  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
-}
-
-/**
-  * @brief  Set the lock level to freeze the
-  *         configuration of several capture/compare parameters.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       the lock mechanism is supported by a timer instance.
-  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
-  * @param  TIMx Timer instance
-  * @param  LockLevel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
-  *         @arg @ref LL_TIM_LOCKLEVEL_1
-  *         @arg @ref LL_TIM_LOCKLEVEL_2
-  *         @arg @ref LL_TIM_LOCKLEVEL_3
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
-}
-
-/**
-  * @brief  Enable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
-  *         CCER         CC6E          LL_TIM_CC_EnableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  SET_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Disable capture/compare channels.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
-  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
-  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
-  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
-  *         CCER         CC6E          LL_TIM_CC_DisableChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  CLEAR_BIT(TIMx->CCER, Channels);
-}
-
-/**
-  * @brief  Indicate whether channel(s) is(are) enabled.
-  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
-  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
-  * @param  TIMx Timer instance
-  * @param  Channels This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
-  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure an output channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
-  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
-  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
-  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
-  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
-  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
-             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
-  * @brief  Define the behavior of the output reference signal OCxREF from which
-  *         OCx and OCxN (when relevant) are derived.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
-  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
-  *         CCMR3        OC6M          LL_TIM_OC_SetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Get the output compare mode of an output channel.
-  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
-  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
-  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
-  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
-  *         CCMR3        OC6M          LL_TIM_OC_GetMode
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCMODE_FROZEN
-  *         @arg @ref LL_TIM_OCMODE_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_TOGGLE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
-  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
-  *         @arg @ref LL_TIM_OCMODE_PWM1
-  *         @arg @ref LL_TIM_OCMODE_PWM2
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
-  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
-  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
-  * @brief  Set the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
-  *         CCER         CC6P          LL_TIM_OC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the polarity of an output channel.
-  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
-  *         CCER         CC6P          LL_TIM_OC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
-  *         @arg @ref LL_TIM_OCPOLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Set the IDLE state of an output channel
-  * @note This function is significant only for the timer instances
-  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
-  *       can be used to check whether or not a timer instance provides
-  *       a break input.
-  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
-  *         CR2         OIS6          LL_TIM_OC_SetIdleState
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  IdleState This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
-  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
-  * @brief  Get the IDLE state of an output channel
-  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
-  *         CR2         OIS6          LL_TIM_OC_GetIdleState
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH1N
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH2N
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH3N
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
-  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
-  * @brief  Enable fast mode for the output channel.
-  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
-  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
-  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Disable fast mode for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
-  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
-  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
-  * @brief  Indicates whether fast mode is enabled for the output channel.
-  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
-  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
-  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
-  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
-  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
-  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
-  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
-  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Disable clearing the output channel on an external event.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
-  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
-  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
-  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
-  * @note This function enables clearing the output channel on an external event.
-  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
-  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance can clear the OCxREF signal on an external event.
-  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
-  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
-  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
-  *         the Ocx and OCxN signals).
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       dead-time insertion feature is supported by a timer instance.
-  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
-  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
-  * @param  TIMx Timer instance
-  * @param  DeadTime between Min_Data=0 and Max_Data=255
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
-}
-
-/**
-  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR1, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR2, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR3, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
-  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR4, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
-  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 5 is supported by a timer instance.
-  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
-}
-
-/**
-  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
-  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 6 is supported by a timer instance.
-  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
-  * @param  TIMx Timer instance
-  * @param  CompareValue between Min_Data=0 and Max_Data=65535
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
-  WRITE_REG(TIMx->CCR6, CompareValue);
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
-  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
-  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 5 is supported by a timer instance.
-  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
-}
-
-/**
-  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
-  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
-  *       output channel 6 is supported by a timer instance.
-  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
-  * @param  TIMx Timer instance
-  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR6));
-}
-
-/**
-  * @brief  Select on which reference signal the OC5REF is combined to.
-  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports the combined 3-phase PWM mode.
-  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
-  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
-  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
-  * @param  TIMx Timer instance
-  * @param  GroupCH5 This parameter can be a combination of the following values:
-  *         @arg @ref LL_TIM_GROUPCH5_NONE
-  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
-  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
-  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
-{
-  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
-  * @{
-  */
-/**
-  * @brief  Configure input channel.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
-  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC1F          LL_TIM_IC_Config\n
-  *         CCMR1        CC2S          LL_TIM_IC_Config\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
-  *         CCMR1        IC2F          LL_TIM_IC_Config\n
-  *         CCMR2        CC3S          LL_TIM_IC_Config\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC3F          LL_TIM_IC_Config\n
-  *         CCMR2        CC4S          LL_TIM_IC_Config\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
-  *         CCMR2        IC4F          LL_TIM_IC_Config\n
-  *         CCER         CC1P          LL_TIM_IC_Config\n
-  *         CCER         CC1NP         LL_TIM_IC_Config\n
-  *         CCER         CC2P          LL_TIM_IC_Config\n
-  *         CCER         CC2NP         LL_TIM_IC_Config\n
-  *         CCER         CC3P          LL_TIM_IC_Config\n
-  *         CCER         CC3NP         LL_TIM_IC_Config\n
-  *         CCER         CC4P          LL_TIM_IC_Config\n
-  *         CCER         CC4NP         LL_TIM_IC_Config
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
-  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
-             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
-             << SHIFT_TAB_ICxx[iChannel]);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Set the active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICActiveInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current active input.
-  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
-  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
-  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the prescaler of input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the current prescaler value acting on an  input channel.
-  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
-  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_ICPSC_DIV1
-  *         @arg @ref LL_TIM_ICPSC_DIV2
-  *         @arg @ref LL_TIM_ICPSC_DIV4
-  *         @arg @ref LL_TIM_ICPSC_DIV8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
-  * @brief  Get the input filter duration.
-  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
-  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
-  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
-  * @brief  Set the input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  ICPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
-             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Get the current input channel polarity.
-  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
-  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
-  * @param  TIMx Timer instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_TIM_IC_POLARITY_RISING
-  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
-  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
-  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
-  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
-          SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
-  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
-  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
-  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance provides an XOR input.
-  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get captured value for input channel 1.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 1 is supported by a timer instance.
-  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
-  * @brief  Get captured value for input channel 2.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 2 is supported by a timer instance.
-  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
-  * @brief  Get captured value for input channel 3.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 3 is supported by a timer instance.
-  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
-  * @brief  Get captured value for input channel 4.
-  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
-  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports a 32 bits counter.
-  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
-  *       input channel 4 is supported by a timer instance.
-  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
-  * @param  TIMx Timer instance
-  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
-  */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
-{
-  return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
-  * @{
-  */
-/**
-  * @brief  Enable external clock mode 2.
-  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Disable external clock mode 2.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
-  * @brief  Indicate whether external clock mode 2 is enabled.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the clock source of the counter clock.
-  * @note when selected clock source is external clock mode 1, the timer input
-  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
-  *       function. This timer input must be configured by calling
-  *       the @ref LL_TIM_IC_Config() function.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode1.
-  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports external clock mode2.
-  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
-  *         SMCR         ECE           LL_TIM_SetClockSource
-  * @param  TIMx Timer instance
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
-  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
-}
-
-/**
-  * @brief  Set the encoder interface mode.
-  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance supports the encoder mode.
-  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
-  * @param  TIMx Timer instance
-  * @param  EncoderMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
-  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
-  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
-  * @{
-  */
-/**
-  * @brief  Set the trigger output (TRGO) used for timer synchronization .
-  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance can operate as a master timer.
-  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
-  * @param  TIMx Timer instance
-  * @param  TimerSynchronization This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TRGO_RESET
-  *         @arg @ref LL_TIM_TRGO_ENABLE
-  *         @arg @ref LL_TIM_TRGO_UPDATE
-  *         @arg @ref LL_TIM_TRGO_CC1IF
-  *         @arg @ref LL_TIM_TRGO_OC1REF
-  *         @arg @ref LL_TIM_TRGO_OC2REF
-  *         @arg @ref LL_TIM_TRGO_OC3REF
-  *         @arg @ref LL_TIM_TRGO_OC4REF
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
-}
-
-/**
-  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
-  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
-  *       whether or not a timer instance can be used for ADC synchronization.
-  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
-  * @param  TIMx Timer Instance
-  * @param  ADCSynchronization This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TRGO2_RESET
-  *         @arg @ref LL_TIM_TRGO2_ENABLE
-  *         @arg @ref LL_TIM_TRGO2_UPDATE
-  *         @arg @ref LL_TIM_TRGO2_CC1F
-  *         @arg @ref LL_TIM_TRGO2_OC1
-  *         @arg @ref LL_TIM_TRGO2_OC2
-  *         @arg @ref LL_TIM_TRGO2_OC3
-  *         @arg @ref LL_TIM_TRGO2_OC4
-  *         @arg @ref LL_TIM_TRGO2_OC5
-  *         @arg @ref LL_TIM_TRGO2_OC6
-  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
-  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
-  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
-  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
-  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
-  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
-{
-  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
-}
-
-/**
-  * @brief  Set the synchronization mode of a slave timer.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
-  * @param  TIMx Timer instance
-  * @param  SlaveMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
-  *         @arg @ref LL_TIM_SLAVEMODE_RESET
-  *         @arg @ref LL_TIM_SLAVEMODE_GATED
-  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
-  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
-}
-
-/**
-  * @brief  Set the selects the trigger input to be used to synchronize the counter.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
-  * @param  TIMx Timer instance
-  * @param  TriggerInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_TS_ITR0
-  *         @arg @ref LL_TIM_TS_ITR1
-  *         @arg @ref LL_TIM_TS_ITR2
-  *         @arg @ref LL_TIM_TS_ITR3
-  *         @arg @ref LL_TIM_TS_TI1F_ED
-  *         @arg @ref LL_TIM_TS_TI1FP1
-  *         @arg @ref LL_TIM_TS_TI2FP2
-  *         @arg @ref LL_TIM_TS_ETRF
-  *         @arg @ref LL_TIM_TS_ITR7 (*)
-  *
-  *      (*)  Value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
-}
-
-/**
-  * @brief  Enable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief  Disable the Master/Slave mode.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
-  * @brief Indicates whether the Master/Slave mode is enabled.
-  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
-  * a timer instance can operate as a slave timer.
-  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure the external trigger (ETR) input.
-  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides an external trigger input.
-  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
-  *         SMCR         ETPS          LL_TIM_ConfigETR\n
-  *         SMCR         ETF           LL_TIM_ConfigETR
-  * @param  TIMx Timer instance
-  * @param  ETRPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
-  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
-  * @param  ETRPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
-  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
-  * @param  ETRFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
-                                      uint32_t ETRFilter)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
-}
-
-/**
-  * @brief  Select the external trigger (ETR) input source.
-  * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
-  *       not a timer instance supports ETR source selection.
-  * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
-  * @param  TIMx Timer instance
-  * @param  ETRSource This parameter can be one of the following values:
-  *         TIM1
-  *
-  *         @arg @ref LL_TIM_ETRSOURCE_GPIO
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP1 (**)
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP2 (**)
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
-  *         @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
-  *         @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
-  *         @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
-  *
-  *         TIM2 (*)
-  *
-  *         @arg @ref LL_TIM_ETRSOURCE_GPIO
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP1
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP2
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
-  *         @arg @ref LL_TIM_ETRSOURCE_LSE
-  *         @arg @ref LL_TIM_ETRSOURCE_MCO (**)
-  *         @arg @ref LL_TIM_ETRSOURCE_MCO2 (**)
-  *
-  *         TIM3
-  *
-  *         @arg @ref LL_TIM_ETRSOURCE_GPIO
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP1 (**)
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP2 (**)
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
-  *
-  *         TIM4 (*)
-  *
-  *         @arg @ref LL_TIM_ETRSOURCE_GPIO
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP1
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP2
-  *         @arg @ref LL_TIM_ETRSOURCE_COMP3 (**)
-  *
-  *  (*) Timer instance not available on all devices \n
-  *  (**) Value not defined in all devices. \n
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
-{
-#if defined(COMP3)
-  uint32_t etrsel_shift = ((ETRSource == LL_TIM_ETRSOURCE_COMP3) ? 1u : 0u);
-  if ((TIMx == TIM1) || (TIMx == TIM2))
-  {
-    MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
-  }
-  else
-  {
-    MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource >> etrsel_shift);
-  }
-#else
-  MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
-#endif /* COMP3 */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Break_Function Break function configuration
-  * @{
-  */
-/**
-  * @brief  Enable the break function.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
-  * @brief  Disable the break function.
-  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
-  * @param  TIMx Timer instance
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
-  * @brief  Configure the break input.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @note Bidirectional mode is only supported by advanced timer instances.
-  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance is an advanced-control timer.
-  * @note In bidirectional mode (BKBID bit set), the Break input is configured both
-  *        in input mode and in open drain output mode. Any active Break event will
-  *        assert a low logic level on the Break input to indicate an internal break
-  *        event to external devices.
-  * @note When bidirectional mode isn't supported, BreakAFMode must be set to
-  *       LL_TIM_BREAK_AFMODE_INPUT.
-  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
-  *         BDTR         BKF           LL_TIM_ConfigBRK\n
-  *         BDTR         BKBID         LL_TIM_ConfigBRK
-  * @param  TIMx Timer instance
-  * @param  BreakPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
-  * @param  BreakFilter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
-  * @param  BreakAFMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
-  *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
-                                      uint32_t BreakAFMode)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
-}
-
-/**
-  * @brief  Disarm the break input (when it operates in bidirectional mode).
-  * @note  The break input can be disarmed only when it is configured in
-  *        bidirectional mode and when when MOE is reset.
-  * @note  Purpose is to be able to have the input voltage back to high-state,
-  *        whatever the time constant on the output .
-  * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
-/**
-  * @brief  Re-arm the break input (when it operates in bidirectional mode).
-  * @note  The Break input is automatically armed as soon as MOE bit is set.
-  * @rmtoll BDTR         BKDSRM        LL_TIM_ReArmBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
-/**
-  * @brief  Enable the break 2 function.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
-}
-
-/**
-  * @brief  Disable the break  2 function.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
-}
-
-/**
-  * @brief  Configure the break 2 input.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @note Bidirectional mode is only supported by advanced timer instances.
-  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance is an advanced-control timer.
-  * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
-  *        in input mode and in open drain output mode. Any active Break event will
-  *        assert a low logic level on the Break 2 input to indicate an internal break
-  *        event to external devices.
-  * @note When bidirectional mode isn't supported, Break2AFMode must be set to
-  *       LL_TIM_BREAK2_AFMODE_INPUT.
-  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
-  *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
-  *         BDTR         BK2BID        LL_TIM_ConfigBRK2
-  * @param  TIMx Timer instance
-  * @param  Break2Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
-  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
-  * @param  Break2Filter This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
-  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
-  * @param  Break2AFMode This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
-  *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
-                                       uint32_t Break2AFMode)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
-}
-
-/**
-  * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
-  * @note  The break 2 input can be disarmed only when it is configured in
-  *        bidirectional mode and when when MOE is reset.
-  * @note  Purpose is to be able to have the input voltage back to high-state,
-  *        whatever the time constant on the output.
-  * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
-/**
-  * @brief  Re-arm the break 2 input (when it operates in bidirectional mode).
-  * @note  The Break 2 input is automatically armed as soon as MOE bit is set.
-  * @rmtoll BDTR         BK2DSRM       LL_TIM_ReArmBRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
-/**
-  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
-  *         BDTR         OSSR          LL_TIM_SetOffStates
-  * @param  TIMx Timer instance
-  * @param  OffStateIdle This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OSSI_DISABLE
-  *         @arg @ref LL_TIM_OSSI_ENABLE
-  * @param  OffStateRun This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OSSR_DISABLE
-  *         @arg @ref LL_TIM_OSSR_ENABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
-{
-  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
-}
-
-/**
-  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
-  * @brief  Disable automatic output (MOE can be set only by software).
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
-  * @brief  Indicate whether automatic output is enabled.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
-  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
-  *       software and is reset in case of break or break2 event
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
-  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
-  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
-  *       software and is reset in case of break or break2 event.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
-  * @brief  Indicates whether outputs are enabled.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable the signals connected to the designated timer break input.
-  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance allows for break input selection.
-  * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
-  *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
-  *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
-  *         AF1          BKCMP3E       LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
-  *         AF2          BK2CMP3E      LL_TIM_EnableBreakInputSource
-  * @param  TIMx Timer instance
-  * @param  BreakInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
-  *
-  *         (*)  Value not defined in all devices. \n
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
-  SET_BIT(*pReg, Source);
-}
-
-/**
-  * @brief  Disable the signals connected to the designated timer break input.
-  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance allows for break input selection.
-  * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
-  *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
-  *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
-  *         AF1          BKCMP3E       LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
-  *         AF2          BK2CMP3E      LL_TIM_DisableBreakInputSource
-  * @param  TIMx Timer instance
-  * @param  BreakInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
-  *
-  *         (*)  Value not defined in all devices. \n
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
-  CLEAR_BIT(*pReg, Source);
-}
-
-/**
-  * @brief  Set the polarity of the break signal for the timer break input.
-  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
-  *       or not a timer instance allows for break input selection.
-  * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF1          BKCMP3P       LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity\n
-  *         AF2          BK2CMP3P      LL_TIM_SetBreakInputSourcePolarity
-  * @param  TIMx Timer instance
-  * @param  BreakInput This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
-  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
-  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3 (*)
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
-  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
-  *
-  *         (*)  Value not defined in all devices. \n
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
-                                                        uint32_t Polarity)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
-  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
-  * @{
-  */
-/**
-  * @brief  Configures the timer DMA burst feature.
-  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
-  *       not a timer instance supports the DMA burst mode.
-  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
-  *         DCR          DBA           LL_TIM_ConfigDMABurst
-  * @param  TIMx Timer instance
-  * @param  DMABurstBaseAddress This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5  
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6  
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1  
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2  
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
-  * @param  DMABurstLength This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
-  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
-{
-  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
-  * @{
-  */
-/**
-  * @brief  Remap TIM inputs (input channel, internal/external triggers).
-  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
-  *       a some timer inputs can be remapped.
-  * @rmtoll TIM1_TISEL    TI1SEL      LL_TIM_SetRemap\n
-  *         TIM1_TISEL    TI2SEL      LL_TIM_SetRemap\n
-  *         TIM2_TISEL    TI1SEL      LL_TIM_SetRemap\n
-  *         TIM2_TISEL    TI2SEL      LL_TIM_SetRemap\n
-  *         TIM3_TISEL    TI1SEL      LL_TIM_SetRemap\n
-  *         TIM3_TISEL    TI2SEL      LL_TIM_SetRemap\n
-  *         TIM4_TISEL    TI1SEL      LL_TIM_SetRemap\n
-  *         TIM4_TISEL    TI2SEL      LL_TIM_SetRemap\n
-  *         TIM4_TISEL    TI3SEL      LL_TIM_SetRemap\n
-  *         TIM14_TISEL   TI1SEL      LL_TIM_SetRemap\n
-  *         TIM15_TISEL   TI1SEL      LL_TIM_SetRemap\n
-  *         TIM15_TISEL   TI2SEL      LL_TIM_SetRemap\n
-  *         TIM16_TISEL   TI1SEL      LL_TIM_SetRemap\n
-  *         TIM17_TISEL   TI1SEL      LL_TIM_SetRemap
-  * @param  TIMx Timer instance
-  * @param  Remap Remap param depends on the TIMx. Description available only
-  *         in CHM version of the User Manual (not in .pdf).
-  *         Otherwise see Reference Manual description of TISEL registers.
-  *
-  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
-  *
-  *         TIM1: any combination of TI1_RMP and TI2_RMP where
-  *
-  *            . . TI1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (**)
-  *
-  *            . . TI2_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM1_TI2_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM1_TI2_RMP_COMP2 (**)
-  *
-  *            . . TI3_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM1_TI3_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM1_TI3_RMP_COMP3 (**)
-  *
-  *         TIM2: any combination of TI1_RMP and TI2_RMP where
-  *
-  *            . . TI1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1 (**)
-  *
-  *            . . TI2_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2 (**)
-  *
-  *            . . TI3_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM2_TI3_RMP_COMP3 (**)
-  *
-  *         TIM3: any combination of TI1_RMP and TI2_RMP where
-  *
-  *            . . TI1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 (**)
-  *
-  *            . . TI2_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2 (**)
-  *
-  *            . . TI3_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3 (**)
-  *
-  *         TIM4: any combination of TI1_RMP, TI2_RMP and TI3_RMP where  (*)
-  *
-  *            . . TI1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1 (**)
-  *
-  *            . . TI2_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2 (**)
-  *
-  *            . . TI3_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM4_TI3_RMP_COMP3 (**)
-  *
-  *         TIM14: one of the following values
-  *
-  *            @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
-  *            @arg @ref LL_TIM_TIM14_TI1_RMP_HSE_32
-  *            @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
-  *            @arg @ref LL_TIM_TIM14_TI1_RMP_MCO2 (**)
-  *
-  *         TIM15: any combination of TI1_RMP and TI2_RMP where
-  *
-  *            . . TI1_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_IC1
-  *            @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_IC1
-  *
-  *            . . TI2_RMP can be one of the following values
-  *            @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_IC2
-  *            @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_IC2
-  *
-  *         TIM16: one of the following values
-  *
-  *            @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
-  *            @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
-  *            @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
-  *            @arg @ref LL_TIM_TIM16_TI1_RMP_MCO2(**)
-  *
-  *         TIM17: one of the following values
-  *
-  *            @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
-  *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
-  *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
-  *            @arg @ref LL_TIM_TIM17_TI1_RMP_HSI48 (**)
-  *            @arg @ref LL_TIM_TIM17_TI1_RMP_MCO2(**)
-  *
-  *  (*) Timer instance not available on all devices \n
-  *  (**) Value not defined in all devices. \n
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
-{
-  MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
-  * @{
-  */
-/**
-  * @brief  Set the OCREF clear input source
-  * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
-  * @note This function can only be used in Output compare and PWM modes.
-  * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
-  * @rmtoll OR1           OCREF_CLR           LL_TIM_SetOCRefClearInputSource
-  * @param  TIMx Timer instance
-  * @param  OCRefClearInputSource This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
-  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP1 (*)
-  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 (*)
-  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP3 (*)
-  *
-  *         (*)  Value not defined in all devices. \n
-  *
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
-{
-  MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
-             ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
-  MODIFY_REG(TIMx->OR1, TIM1_OR1_OCREF_CLR, OCRefClearInputSource);
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
-  * @{
-  */
-/**
-  * @brief  Clear the update interrupt flag (UIF).
-  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
-}
-
-/**
-  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
-  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
-  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
-  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
-  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
-  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
-  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
-  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
-  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
-  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
-  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
-  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
-  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the commutation interrupt flag (COMIF).
-  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
-}
-
-/**
-  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
-  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the trigger interrupt flag (TIF).
-  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
-}
-
-/**
-  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
-  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the break interrupt flag (BIF).
-  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
-}
-
-/**
-  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
-  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the break 2 interrupt flag (B2IF).
-  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
-}
-
-/**
-  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
-  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
-  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
-  *         (Capture/Compare 1 interrupt is pending).
-  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
-  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
-  *         (Capture/Compare 2 over-capture interrupt is pending).
-  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
-  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
-  *         (Capture/Compare 3 over-capture interrupt is pending).
-  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
-  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
-}
-
-/**
-  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
-  *         (Capture/Compare 4 over-capture interrupt is pending).
-  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear the system break interrupt flag (SBIF).
-  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
-{
-  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
-}
-
-/**
-  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
-  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_IT_Management IT-Management
-  * @{
-  */
-/**
-  * @brief  Enable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Disable update interrupt (UIE).
-  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
-  * @brief  Indicates whether the update interrupt (UIE) is enabled.
-  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  interrupt (CC1IE).
-  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
-  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  interrupt (CC2IE).
-  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
-  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  interrupt (CC3IE).
-  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
-  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  interrupt (CC4IE).
-  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
-  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable commutation interrupt (COMIE).
-  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
-  * @brief  Disable commutation interrupt (COMIE).
-  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
-  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
-  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TIE).
-  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
-  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable break interrupt (BIE).
-  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
-  * @brief  Disable break interrupt (BIE).
-  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
-  * @brief  Indicates whether the break interrupt (BIE) is enabled.
-  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
-  * @{
-  */
-/**
-  * @brief  Enable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Disable update DMA request (UDE).
-  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
-  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
-  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 1 DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Disable capture/compare 1  DMA request (CC1DE).
-  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
-  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 2 DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Disable capture/compare 2  DMA request (CC2DE).
-  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
-  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 3 DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Disable capture/compare 3  DMA request (CC3DE).
-  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
-  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable capture/compare 4 DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Disable capture/compare 4  DMA request (CC4DE).
-  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
-  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
-  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable commutation DMA request (COMDE).
-  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
-  * @brief  Disable commutation DMA request (COMDE).
-  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
-  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
-  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Disable trigger interrupt (TDE).
-  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
-  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
-  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
-  * @param  TIMx Timer instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
-  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
-  * @{
-  */
-/**
-  * @brief  Generate an update event.
-  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_UG);
-}
-
-/**
-  * @brief  Generate Capture/Compare 1 event.
-  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 2 event.
-  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 3 event.
-  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
-}
-
-/**
-  * @brief  Generate Capture/Compare 4 event.
-  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
-}
-
-/**
-  * @brief  Generate commutation event.
-  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
-}
-
-/**
-  * @brief  Generate trigger event.
-  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_TG);
-}
-
-/**
-  * @brief  Generate break event.
-  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_BG);
-}
-
-/**
-  * @brief  Generate break 2 event.
-  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
-  * @param  TIMx Timer instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
-{
-  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
-  * @{
-  */
-
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32G0xx_LL_TIM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_usart.h

@@ -1,4403 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_usart.h
-  * @author  MCD Application Team
-  * @brief   Header file of USART LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_USART_H
-#define STM32G0xx_LL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6)
-
-/** @defgroup USART_LL USART
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Variables USART Private Variables
-  * @{
-  */
-/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
-static const uint32_t USART_PRESCALER_TAB[] =
-{
-  1UL,
-  2UL,
-  4UL,
-  6UL,
-  8UL,
-  10UL,
-  12UL,
-  16UL,
-  32UL,
-  64UL,
-  128UL,
-  256UL
-};
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_Private_Macros USART Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_ES_INIT USART Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL USART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
-                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetPrescaler().*/
-
-  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetBaudRate().*/
-
-  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetDataWidth().*/
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetStopBitsLength().*/
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetParity().*/
-
-  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetTransferDirection().*/
-
-  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetHWFlowCtrl().*/
-
-  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
-                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
-
-                                           This feature can be modified afterwards using unitary
-                                           function @ref LL_USART_SetOverSampling().*/
-
-} LL_USART_InitTypeDef;
-
-/**
-  * @brief LL USART Clock Init Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
-
-                                           USART HW configuration can be modified afterwards using unitary functions
-                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
-
-                                           USART HW configuration can be modified afterwards using unitary
-                                           functions @ref LL_USART_SetClockPolarity().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
-
-                                           USART HW configuration can be modified afterwards using unitary
-                                           functions @ref LL_USART_SetClockPhase().
-                                           For more details, refer to description of this function. */
-
-  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
-
-                                           USART HW configuration can be modified afterwards using unitary
-                                           functions @ref LL_USART_SetLastClkPulseOutput().
-                                           For more details, refer to description of this function. */
-
-} LL_USART_ClockInitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Constants USART Exported Constants
-  * @{
-  */
-
-/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_USART_WriteReg function
-  * @{
-  */
-#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
-#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
-#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected clear flag */
-#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
-#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
-#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
-#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
-#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
-#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
-#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
-#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
-#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
-#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun clear flag */
-#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
-#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_USART_ReadReg function
-  * @{
-  */
-#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
-#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
-#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
-#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
-#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
-#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
-#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
-#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
-#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
-#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
-#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
-#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
-#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
-#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
-#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
-#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
-#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
-#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
-#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
-#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
-#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
-#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
-#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
-#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
-#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
-#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
-#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
-#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
-  * @{
-  */
-#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
-#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
-#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
-#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
-#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
-#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
-#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
-#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
-#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
-#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
-#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
-#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
-#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
-#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
-#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
-#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
-#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
-  * @{
-  */
-#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
-#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
-#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
-#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
-#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
-#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DIRECTION Communication Direction
-  * @{
-  */
-#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
-#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PARITY Parity Control
-  * @{
-  */
-#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
-#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
-#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_WAKEUP Wakeup
-  * @{
-  */
-#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
-#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
-  * @{
-  */
-#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
-#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EC_CLOCK Clock Signal
-  * @{
-  */
-
-#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
-#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
-  * @{
-  */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
-#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PHASE Clock Phase
-  * @{
-  */
-#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
-#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
-#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
-  * @{
-  */
-#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not divided   */
-#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock divided by 2  */
-#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock divided by 4  */
-#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 6  */
-#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock divided by 8  */
-#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 10 */
-#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 12 */
-#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
-#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock divided by 32 */
-#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 64 */
-#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 128 */
-#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_STOPBITS Stop Bits
-  * @{
-  */
-#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
-#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
-#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
-  * @{
-  */
-#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
-#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
-  * @{
-  */
-#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
-#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
-  * @{
-  */
-#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
-#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
-  * @{
-  */
-#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
-#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_BITORDER Bit Order
-  * @{
-  */
-#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
-#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
-  * @{
-  */
-#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
-#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
-#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
-#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
-  * @{
-  */
-#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
-#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
-  * @{
-  */
-#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
-#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
-  * @{
-  */
-#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
-#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
-#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
-  * @{
-  */
-#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
-#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
-  * @{
-  */
-#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
-#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
-  * @{
-  */
-#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
-#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
-  * @{
-  */
-#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
-#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Macros USART Exported Macros
-  * @{
-  */
-
-/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
-  * @{
-  */
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
-  */
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
-  (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
-    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
-  */
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
-  ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
-    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_LL_Exported_Functions USART Exported Functions
-  * @{
-  */
-
-/** @defgroup USART_LL_EF_Configuration Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  USART Enable
-  * @rmtoll CR1          UE            LL_USART_Enable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  USART Disable (all USART prescalers and outputs are disabled)
-  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
-  *         and current operations are discarded. The configuration of the USART is kept, but all the status
-  *         flags, in the USARTx_ISR are set to their default values.
-  * @rmtoll CR1          UE            LL_USART_Disable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  Indicate if USART is enabled
-  * @rmtoll CR1          UE            LL_USART_IsEnabled
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  FIFO Mode Enable
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
-  * @brief  FIFO Mode Disable
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
-}
-
-/**
-  * @brief  Indicate if FIFO Mode is enabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure TX FIFO Threshold
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
-  * @param  USARTx USART Instance
-  * @param  Threshold This parameter can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
-}
-
-/**
-  * @brief  Return TX FIFO Threshold Configuration
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
-}
-
-/**
-  * @brief  Configure RX FIFO Threshold
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
-  * @param  USARTx USART Instance
-  * @param  Threshold This parameter can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
-}
-
-/**
-  * @brief  Return RX FIFO Threshold Configuration
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  */
-__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
-}
-
-/**
-  * @brief  Configure TX and RX FIFOs Threshold
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
-  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
-  * @param  USARTx USART Instance
-  * @param  TXThreshold This parameter can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  * @param  RXThreshold This parameter can be one of the following values:
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
-  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
-                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
-}
-
-/**
-  * @brief  USART enabled in STOP Mode.
-  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
-  *         USART clock selection is HSI or LSE in RCC.
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  USART disabled in STOP Mode.
-  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
-}
-
-/**
-  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
-  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Receiver Disable
-  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Transmitter Enable
-  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Transmitter Disable
-  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Configure simultaneously enabled/disabled states
-  *         of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
-  *         CR1          TE            LL_USART_SetTransferDirection
-  * @param  USARTx USART Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
-  * @brief  Return enabled/disabled states of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
-  *         CR1          TE            LL_USART_GetTransferDirection
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
-  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
-  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
-  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
-  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
-  * @rmtoll CR1          PS            LL_USART_SetParity\n
-  *         CR1          PCE           LL_USART_SetParity
-  * @param  USARTx USART Instance
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
-  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
-  * @rmtoll CR1          PS            LL_USART_GetParity\n
-  *         CR1          PCE           LL_USART_GetParity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
-  * @brief  Set Receiver Wake Up method from Mute mode.
-  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @param  Method This parameter can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
-  * @brief  Return Receiver Wake Up method from Mute mode
-  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
-  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
-  *         CR1          M1            LL_USART_SetDataWidth
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_7B
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
-  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
-  *         CR1          M1            LL_USART_GetDataWidth
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_7B
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
-}
-
-/**
-  * @brief  Allow switch between Mute Mode and Active mode
-  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
-  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
-}
-
-/**
-  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
-  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Oversampling to 8-bit or 16-bit mode
-  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
-  * @param  USARTx USART Instance
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
-}
-
-/**
-  * @brief  Return Oversampling mode
-  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
-}
-
-/**
-  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @param  LastBitClockPulse This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
-}
-
-/**
-  * @brief  Retrieve Clock pulse of the last data bit output configuration
-  *         (Last bit Clock pulse output to the SCLK pin or not)
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
-}
-
-/**
-  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
-  * @param  USARTx USART Instance
-  * @param  ClockPhase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
-}
-
-/**
-  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
-}
-
-/**
-  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
-  * @param  USARTx USART Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
-}
-
-/**
-  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
-}
-
-/**
-  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
-  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
-  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
-  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
-  *         CR2          CPOL          LL_USART_ConfigClock\n
-  *         CR2          LBCL          LL_USART_ConfigClock
-  * @param  USARTx USART Instance
-  * @param  Phase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @param  LBCPOutput This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
-}
-
-/**
-  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
-}
-
-/**
-  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  */
-__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
-}
-
-/**
-  * @brief  Enable Clock output on SCLK pin
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Disable Clock output on SCLK pin
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Indicate if Clock output on SCLK pin is enabled
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
-  * @param  USARTx USART Instance
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Retrieve the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
-}
-
-/**
-  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
-  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
-  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
-  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
-  *         CR1          PCE           LL_USART_ConfigCharacter\n
-  *         CR1          M0            LL_USART_ConfigCharacter\n
-  *         CR1          M1            LL_USART_ConfigCharacter\n
-  *         CR2          STOP          LL_USART_ConfigCharacter
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_7B
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
-                                              uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Configure TX/RX pins swapping setting.
-  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
-  * @param  USARTx USART Instance
-  * @param  SwapConfig This parameter can be one of the following values:
-  *         @arg @ref LL_USART_TXRX_STANDARD
-  *         @arg @ref LL_USART_TXRX_SWAPPED
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
-}
-
-/**
-  * @brief  Retrieve TX/RX pins swapping configuration.
-  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_TXRX_STANDARD
-  *         @arg @ref LL_USART_TXRX_SWAPPED
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
-}
-
-/**
-  * @brief  Configure RX pin active level logic
-  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
-  * @param  USARTx USART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve RX pin active level logic configuration
-  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
-}
-
-/**
-  * @brief  Configure TX pin active level logic
-  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
-  * @param  USARTx USART Instance
-  * @param  PinInvMethod This parameter can be one of the following values:
-  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
-}
-
-/**
-  * @brief  Retrieve TX pin active level logic configuration
-  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
-  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
-}
-
-/**
-  * @brief  Configure Binary data logic.
-  * @note   Allow to define how Logical data from the data register are send/received :
-  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
-  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
-  * @param  USARTx USART Instance
-  * @param  DataLogic This parameter can be one of the following values:
-  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
-}
-
-/**
-  * @brief  Retrieve Binary data configuration
-  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
-  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
-}
-
-/**
-  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
-  * @param  USARTx USART Instance
-  * @param  BitOrder This parameter can be one of the following values:
-  *         @arg @ref LL_USART_BITORDER_LSBFIRST
-  *         @arg @ref LL_USART_BITORDER_MSBFIRST
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
-}
-
-/**
-  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
-  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
-  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
-  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_BITORDER_LSBFIRST
-  *         @arg @ref LL_USART_BITORDER_MSBFIRST
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
-}
-
-/**
-  * @brief  Enable Auto Baud-Rate Detection
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
-  * @brief  Disable Auto Baud-Rate Detection
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
-}
-
-/**
-  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Auto Baud-Rate mode bits
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
-  * @param  USARTx USART Instance
-  * @param  AutoBaudRateMode This parameter can be one of the following values:
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
-}
-
-/**
-  * @brief  Return Auto Baud-Rate mode
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
-  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
-  */
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
-}
-
-/**
-  * @brief  Enable Receiver Timeout
-  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
-  * @brief  Disable Receiver Timeout
-  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
-}
-
-/**
-  * @brief  Indicate if Receiver Timeout feature is enabled
-  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Address of the USART node.
-  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with address mark detection.
-  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
-  *         (b7-b4 should be set to 0)
-  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
-  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with 7-bit address mark detection.
-  *         The MSB of the character sent by the transmitter should be equal to 1.
-  *         It may also be used for character detection during normal reception,
-  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
-  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
-  *         value and CMF flag is set on match)
-  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
-  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
-  * @param  USARTx USART Instance
-  * @param  AddressLen This parameter can be one of the following values:
-  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
-  * @param  NodeAddress 4 or 7 bit Address of the USART node.
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
-             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
-}
-
-/**
-  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
-  * @note   If 4-bit Address Detection is selected in ADDM7,
-  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
-  *         If 7-bit Address Detection is selected in ADDM7,
-  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
-  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
-  * @param  USARTx USART Instance
-  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
-}
-
-/**
-  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
-  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
-  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
-}
-
-/**
-  * @brief  Enable RTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Disable RTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Enable CTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Disable CTS HW Flow Control
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Configure HW Flow Control mode (both CTS and RTS)
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @param  HardwareFlowControl This parameter can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
-  * @brief  Return HW Flow Control configuration (both CTS and RTS)
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
-  * @brief  Enable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Disable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Indicate if One bit sampling method is enabled
-  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Disable Overrun detection
-  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
-}
-
-/**
-  * @brief  Indicate if Overrun detection is enabled
-  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
-  * @param  USARTx USART Instance
-  * @param  Type This parameter can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
-}
-
-/**
-  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
-  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
-  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
-}
-
-/**
-  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
-  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
-  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
-  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
-  *         (Baud rate value != 0)
-  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
-  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  PrescalerValue This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @param  BaudRate Baud Rate
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
-                                          uint32_t OverSampling,
-                                          uint32_t BaudRate)
-{
-  uint32_t usartdiv;
-  uint32_t brrtemp;
-
-  if (PrescalerValue > LL_USART_PRESCALER_DIV256)
-  {
-    /* Do not overstep the size of USART_PRESCALER_TAB */
-  }
-  else if (BaudRate == 0U)
-  {
-    /* Can Not divide per 0 */
-  }
-  else if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
-    brrtemp = usartdiv & 0xFFF0U;
-    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
-    USARTx->BRR = brrtemp;
-  }
-  else
-  {
-    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
-  }
-}
-
-/**
-  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
-  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
-  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
-  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
-  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  PrescalerValue This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PRESCALER_DIV1
-  *         @arg @ref LL_USART_PRESCALER_DIV2
-  *         @arg @ref LL_USART_PRESCALER_DIV4
-  *         @arg @ref LL_USART_PRESCALER_DIV6
-  *         @arg @ref LL_USART_PRESCALER_DIV8
-  *         @arg @ref LL_USART_PRESCALER_DIV10
-  *         @arg @ref LL_USART_PRESCALER_DIV12
-  *         @arg @ref LL_USART_PRESCALER_DIV16
-  *         @arg @ref LL_USART_PRESCALER_DIV32
-  *         @arg @ref LL_USART_PRESCALER_DIV64
-  *         @arg @ref LL_USART_PRESCALER_DIV128
-  *         @arg @ref LL_USART_PRESCALER_DIV256
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval Baud Rate
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
-                                              uint32_t OverSampling)
-{
-  uint32_t usartdiv;
-  uint32_t brrresult = 0x0U;
-  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
-
-  usartdiv = USARTx->BRR;
-
-  if (usartdiv == 0U)
-  {
-    /* Do not perform a division by 0 */
-  }
-  else if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
-    if (usartdiv != 0U)
-    {
-      brrresult = (periphclkpresc * 2U) / usartdiv;
-    }
-  }
-  else
-  {
-    if ((usartdiv & 0xFFFFU) != 0U)
-    {
-      brrresult = periphclkpresc / usartdiv;
-    }
-  }
-  return (brrresult);
-}
-
-/**
-  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
-  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
-  * @param  USARTx USART Instance
-  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
-{
-  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
-}
-
-/**
-  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
-  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
-  */
-__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
-}
-
-/**
-  * @brief  Set Block Length value in reception
-  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
-  * @param  USARTx USART Instance
-  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
-{
-  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
-}
-
-/**
-  * @brief  Get Block Length value in reception
-  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
-  * @{
-  */
-
-/**
-  * @brief  Enable IrDA mode
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_EnableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Disable IrDA mode
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_DisableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Indicate if IrDA mode is enabled
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Configure IrDA Power Mode (Normal or Low Power)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_IRDA_POWER_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
-}
-
-/**
-  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
-}
-
-/**
-  * @brief  Set Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
-}
-
-/**
-  * @brief  Return Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Smartcard NACK transmission
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Disable Smartcard NACK transmission
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Indicate if Smartcard NACK transmission is enabled
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable Smartcard mode
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Disable Smartcard mode
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Indicate if Smartcard mode is enabled
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
-  *         In transmission mode, it specifies the number of automatic retransmission retries, before
-  *         generating a transmission error (FE bit set).
-  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
-  *         reception error (RXNE and PE bits set)
-  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
-  * @param  USARTx USART Instance
-  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
-}
-
-/**
-  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
-  * @param  USARTx USART Instance
-  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
-}
-
-/**
-  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
-}
-
-/**
-  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
-{
-  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
-}
-
-/**
-  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Single Wire Half-Duplex mode
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Disable Single Wire Half-Duplex mode
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
-  * @{
-  */
-/**
-  * @brief  Enable SPI Synchronous Slave mode
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
-}
-
-/**
-  * @brief  Disable SPI Synchronous Slave mode
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
-}
-
-/**
-  * @brief  Indicate if  SPI Synchronous Slave mode is enabled
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable SPI Slave Selection using NSS input pin
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @note   SPI Slave Selection depends on NSS input pin
-  *         (The slave is selected when NSS is low and deselected when NSS is high).
-  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
-}
-
-/**
-  * @brief  Disable SPI Slave Selection using NSS input pin
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @note   SPI Slave will be always selected and NSS input pin will be ignored.
-  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
-}
-
-/**
-  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
-  * @{
-  */
-
-/**
-  * @brief  Set LIN Break Detection Length
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @param  LINBDLength This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
-}
-
-/**
-  * @brief  Return LIN Break Detection Length
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
-}
-
-/**
-  * @brief  Enable LIN mode
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Disable LIN mode
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Indicate if LIN mode is enabled
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
-  * @{
-  */
-
-/**
-  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
-  * @param  USARTx USART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Return DEDT (Driver Enable De-Assertion Time)
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
-  * @param  USARTx USART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
-}
-
-/**
-  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
-  * @param  USARTx USART Instance
-  * @param  Time Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Return DEAT (Driver Enable Assertion Time)
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
-  * @param  USARTx USART Instance
-  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
-}
-
-/**
-  * @brief  Enable Driver Enable (DE) Mode
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Disable Driver Enable (DE) Mode
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
-}
-
-/**
-  * @brief  Indicate if Driver Enable (DE) Mode is enabled
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Select Driver Enable Polarity
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
-  * @param  USARTx USART Instance
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DE_POLARITY_HIGH
-  *         @arg @ref LL_USART_DE_POLARITY_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
-}
-
-/**
-  * @brief  Return Driver Enable Polarity
-  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
-  *         Driver Enable feature is supported by the USARTx instance.
-  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DE_POLARITY_HIGH
-  *         @arg @ref LL_USART_DE_POLARITY_LOW
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
-  * @{
-  */
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
-  * @note   In UART mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Asynchronous Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
-  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
-{
-  /* In Asynchronous mode, the following bits must be kept cleared:
-  - LINEN, CLKEN bits in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
-  * @note   In Synchronous mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the USART in Synchronous mode.
-  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  * @note   Other remaining configurations items related to Synchronous Mode
-  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
-  *         CR3          IREN          LL_USART_ConfigSyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
-{
-  /* In Synchronous mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-  /* set the UART/USART in Synchronous mode */
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
-  * @note   In LIN mode, the following bits must be kept cleared:
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also set the UART/USART in LIN mode.
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
-  * @note   Other remaining configurations items related to LIN Mode
-  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
-  *         CR2          STOP          LL_USART_ConfigLINMode\n
-  *         CR2          LINEN         LL_USART_ConfigLINMode\n
-  *         CR3          IREN          LL_USART_ConfigLINMode\n
-  *         CR3          SCEN          LL_USART_ConfigLINMode\n
-  *         CR3          HDSEL         LL_USART_ConfigLINMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
-{
-  /* In LIN mode, the following bits must be kept cleared:
-  - STOP and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* Set the UART/USART in LIN mode */
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
-  * @note   In Half Duplex mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *         This function also sets the UART/USART in Half Duplex mode.
-  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
-  * @note   Other remaining configurations items related to Half Duplex Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
-{
-  /* In Half Duplex mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
-  /* set the UART/USART in Half Duplex mode */
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
-  * @note   In Smartcard mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also configures Stop bits to 1.5 bits and
-  *         sets the USART in Smartcard mode (SCEN bit).
-  *         Clock Output is also enabled (CLKEN).
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
-  * @note   Other remaining configurations items related to Smartcard Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
-  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
-  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
-{
-  /* In Smartcard mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - IREN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
-  /* Configure Stop bits to 1.5 bits */
-  /* Synchronous mode is activated by default */
-  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
-  /* set the UART/USART in Smartcard mode */
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
-  * @note   In IRDA mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the UART/USART in IRDA mode (IREN bit).
-  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
-  * @note   Other remaining configurations items related to Irda Mode
-  *         (as Baud Rate, Word length, Power mode, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
-  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
-  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
-  *         CR3          IREN          LL_USART_ConfigIrdaMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
-{
-  /* In IRDA mode, the following bits must be kept cleared:
-  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-  - SCEN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* set the UART/USART in IRDA mode */
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
-  *         (several USARTs connected in a network, one of the USARTs can be the master,
-  *         its TX output connected to the RX inputs of the other slaves USARTs).
-  * @note   In MultiProcessor mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Multi processor Mode
-  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
-  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
-{
-  /* In Multi Processor mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
-  */
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the USART Parity Error Flag is set or not
-  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Framing Error Flag is set or not
-  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Noise error detected Flag is set or not
-  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART OverRun Error Flag is set or not
-  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART IDLE line detected Flag is set or not
-  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
-
-/**
-  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Flag is set or not
-  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
-
-/**
-  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Flag is set or not
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART CTS interrupt Flag is set or not
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART CTS Flag is set or not
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receiver Time Out Flag is set or not
-  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART End Of Block Flag is set or not
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the SPI Slave Underrun error flag is set or not
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Busy Flag is set or not
-  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Character Match Flag is set or not
-  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Send Break Flag is set or not
-  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
-  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
-  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART TX FIFO Empty Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART RX FIFO Full Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
-  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART TX FIFO Threshold Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART RX FIFO Threshold Flag is set or not
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Clear Parity Error Flag
-  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
-}
-
-/**
-  * @brief  Clear Framing Error Flag
-  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
-}
-
-/**
-  * @brief  Clear Noise Error detected Flag
-  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_NECF);
-}
-
-/**
-  * @brief  Clear OverRun Error Flag
-  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
-}
-
-/**
-  * @brief  Clear IDLE line detected Flag
-  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
-}
-
-/**
-  * @brief  Clear TX FIFO Empty Flag
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
-}
-
-/**
-  * @brief  Clear Transmission Complete Flag
-  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
-}
-
-/**
-  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
-  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
-}
-
-/**
-  * @brief  Clear LIN Break Detection Flag
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
-}
-
-/**
-  * @brief  Clear CTS Interrupt Flag
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
-}
-
-/**
-  * @brief  Clear Receiver Time Out Flag
-  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
-}
-
-/**
-  * @brief  Clear End Of Block Flag
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
-}
-
-/**
-  * @brief  Clear SPI Slave Underrun Flag
-  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
-  *         SPI Slave mode feature is supported by the USARTx instance.
-  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
-}
-
-/**
-  * @brief  Clear Character Match Flag
-  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
-}
-
-/**
-  * @brief  Clear Wake Up from stop mode Flag
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
-
-/**
-  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
-  * @brief  Enable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
-
-/**
-  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
-  * @brief  Enable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Enable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
-  * @brief  Enable Receiver Timeout Interrupt
-  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
-  * @brief  Enable End Of Block Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
-  * @brief  Enable TX FIFO Empty Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
-  * @brief  Enable RX FIFO Full Interrupt
-  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
-  * @brief  Enable LIN Break Detection Interrupt
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Enable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Enable CTS Interrupt
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Enable Wake Up from Stop Mode Interrupt
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
-  * @brief  Enable TX FIFO Threshold Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
-  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
-}
-
-/**
-  * @brief  Enable RX FIFO Threshold Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
-  * @brief  Disable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/* Legacy define */
-#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
-
-/**
-  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
-}
-
-/**
-  * @brief  Disable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/* Legacy define */
-#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
-
-/**
-  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
-}
-
-/**
-  * @brief  Disable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Disable Character Match Interrupt
-  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
-}
-
-/**
-  * @brief  Disable Receiver Timeout Interrupt
-  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
-}
-
-/**
-  * @brief  Disable End Of Block Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
-}
-
-/**
-  * @brief  Disable TX FIFO Empty Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
-}
-
-/**
-  * @brief  Disable RX FIFO Full Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
-}
-
-/**
-  * @brief  Disable LIN Break Detection Interrupt
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Disable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
-  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Disable CTS Interrupt
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Disable Wake Up from Stop Mode Interrupt
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
-}
-
-/**
-  * @brief  Disable TX FIFO Threshold Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
-}
-
-/**
-  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
-}
-
-/**
-  * @brief  Disable RX FIFO Threshold Interrupt
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
-}
-
-/**
-  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
-  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
-
-/**
-  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
-}
-
-/* Legacy define */
-#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
-
-/**
-  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
-  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
-  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
-  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Error Interrupt is enabled or disabled.
-  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
-  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
-  *         Wake-up from Stop mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
-  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_DMA_Management DMA_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Disable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for reception
-  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Disable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for transmission
-  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Enable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Disable DMA Disabling on Reception Error
-  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
-}
-
-/**
-  * @brief  Indicate if DMA Disabling on Reception Error is disabled
-  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
-{
-  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
-  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
-  * @param  USARTx USART Instance
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
-  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
-{
-  uint32_t data_reg_addr;
-
-  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
-  {
-    /* return address of TDR register */
-    data_reg_addr = (uint32_t) &(USARTx->TDR);
-  }
-  else
-  {
-    /* return address of RDR register */
-    data_reg_addr = (uint32_t) &(USARTx->RDR);
-  }
-
-  return data_reg_addr;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
-  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
-{
-  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
-}
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
-  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
-  */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
-{
-  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
-  * @rmtoll TDR          TDR           LL_USART_TransmitData8
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
-{
-  USARTx->TDR = Value;
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
-  * @rmtoll TDR          TDR           LL_USART_TransmitData9
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
-{
-  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Execution Execution
-  * @{
-  */
-
-/**
-  * @brief  Request an Automatic Baud Rate measurement on next received data frame
-  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
-  *         Auto Baud Rate detection feature is supported by the USARTx instance.
-  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
-}
-
-/**
-  * @brief  Request Break sending
-  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
-}
-
-/**
-  * @brief  Put USART in mute mode and set the RWU flag
-  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
-}
-
-/**
-  * @brief  Request a Receive Data and FIFO flush
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @note   Allows to discard the received data without reading them, and avoid an overrun
-  *         condition.
-  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
-}
-
-/**
-  * @brief  Request a Transmit data and FIFO flush
-  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
-  *         FIFO mode feature is supported by the USARTx instance.
-  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
-void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* USART1 || USART2 || USART3 || USART4 || USART5 || USART6 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_utils.h

@@ -1,345 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_utils.h
-  * @author  MCD Application Team
-  * @brief   Header file of UTILS LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL UTILS driver contains a set of generic APIs that can be
-    used by user:
-      (+) Device electronic signature
-      (+) Timing functions
-      (+) PLL configuration functions
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32G0xx_LL_UTILS_H
-#define STM32G0xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup UTILS_LL UTILS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
-  * @{
-  */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY                  0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS              UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
-
-/**
- * @brief Package data register base address
- */
-#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
-  * @{
-  */
-/**
-  * @brief  UTILS PLL structure definition
-  */
-typedef struct
-{
-  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
-                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
-  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
-                        This parameter must be a number between Min_Data = 8 and Max_Data = 86
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
-  uint32_t PLLR;   /*!< Division for the main system clock.
-                        This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-} LL_UTILS_PLLInitTypeDef;
-
-/**
-  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAHBPrescaler(). */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB1Prescaler(). */
-} LL_UTILS_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
-  * @{
-  */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
-  * @{
-  */
-#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
-#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
-  * @{
-  */
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define LL_UTILS_PACKAGETYPE_QFP100         0x00000000U /*!< LQFP100  package type                               */
-#define LL_UTILS_PACKAGETYPE_QFN32_GP       0x00000001U /*!< LQFP32/UFQFPN32 General purpose (GP)                */
-#define LL_UTILS_PACKAGETYPE_QFN32_N        0x00000002U /*!< LQFP32/UFQFPN32 N-version                           */
-#define LL_UTILS_PACKAGETYPE_QFN48_GP       0x00000004U /*!< LQFP48/UFQPN48 General purpose (GP)                 */
-#define LL_UTILS_PACKAGETYPE_QFN48_N        0x00000005U /*!< LQFP48/UFQPN48 N-version                            */
-#define LL_UTILS_PACKAGETYPE_WLCSP52        0x00000006U /*!< WLCSP52                                             */
-#define LL_UTILS_PACKAGETYPE_QFN64_GP       0x00000007U /*!< LQFP64 General purpose (GP)                         */
-#define LL_UTILS_PACKAGETYPE_QFN64_N        0x00000008U /*!< LQFP64 N-version                                    */
-#define LL_UTILS_PACKAGETYPE_BGA64_N        0x0000000AU /*!< UFBGA64 N-version                                   */
-#define LL_UTILS_PACKAGETYPE_QFP80          0x0000000BU /*!< LQFP80  package type                                */
-#define LL_UTILS_PACKAGETYPE_BGA100         0x0000000CU /*!< UBGA100  package type                               */
-#elif defined(STM32G061xx) || defined(STM32G051xx) || defined(STM32G050xx) || defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
-#define LL_UTILS_PACKAGETYPE_SO8            0x00000001U /*!< SO8 package type                                    */
-#define LL_UTILS_PACKAGETYPE_WLCSP18        0x00000002U /*!< WLCSP18 package type                                */
-#define LL_UTILS_PACKAGETYPE_TSSOP20        0x00000003U /*!< TSSOP20 package type                                */
-#define LL_UTILS_PACKAGETYPE_QFP28          0x00000004U /*!< UFQFPN28 package type                               */
-#define LL_UTILS_PACKAGETYPE_QFN32          0x00000005U /*!< UFQFPN32 / LQFP32 package type                      */
-#define LL_UTILS_PACKAGETYPE_QFN48          0x00000007U /*!< UFQFPN48 / LQFP48 package type                      */
-#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
-#define LL_UTILS_PACKAGETYPE_QFN28_GP       0x00000000U /*!< UFQFPN28 general purpose (GP) package type          */
-#define LL_UTILS_PACKAGETYPE_QFN28_PD       0x00000001U /*!< UFQFPN28 Power Delivery (PD)                        */
-#define LL_UTILS_PACKAGETYPE_QFN32_GP       0x00000004U /*!< UFQFPN32 / LQFP32 general purpose (GP) package type */
-#define LL_UTILS_PACKAGETYPE_QFN32_PD       0x00000005U /*!< UFQFPN32 / LQFP32 Power Delivery (PD) package type  */
-#define LL_UTILS_PACKAGETYPE_QFN48          0x00000008U /*!< UFQFPN48 / LQFP488 package type                     */
-#define LL_UTILS_PACKAGETYPE_QFP64          0x0000000CU /*!< LQPF64 package type                                 */
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
-  * @{
-  */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
-  * @{
-  */
-
-/**
-  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
-  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
-}
-
-/**
-  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
-}
-
-/**
-  * @brief  Get Flash memory size
-  * @note   This bitfield indicates the size of the device Flash memory expressed in
-  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
-  * @retval FLASH_SIZE[15:0]: Flash memory size
-  */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
-}
-
-/**
-  * @brief  Get Package type
-  * @retval PKG[3:0]: Package type - This parameter can be a value of @ref UTILS_EC_PACKAGETYPE
-  * @if defined(STM32G0C1xx)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFP100
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32_GP
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32_N
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48_GP
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48_N
-  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP52
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN64_GP
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN64_N
-  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA64_N
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFP80
-  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA100
-  * @elif defined(STM32G061xx) || defined(STM32G041xx)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_SO8
-  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP18
-  *         @arg @ref LL_UTILS_PACKAGETYPE_TSSOP20
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFP28
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48
-  * @elif defined(STM32G081xx)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN28_GP
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN28_PD
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32_GP
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN32_PD
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFN48
-  *         @arg @ref LL_UTILS_PACKAGETYPE_QFP64
-  * @endif
-  *
-  */
-__STATIC_INLINE uint32_t LL_GetPackageType(void)
-{
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-  return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
-#else
-  return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0xFU);
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
-  * @{
-  */
-
-/**
-  * @brief  This function configures the Cortex-M SysTick source of the time base.
-  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
-  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
-  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
-  * @param  Ticks Number of ticks
-  * @retval None
-  */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
-  /* Configure the SysTick to have interrupt in 1ms time base */
-  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
-  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
-}
-
-void        LL_Init1msTick(uint32_t HCLKFrequency);
-void        LL_mDelay(uint32_t Delay);
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
-  * @{
-  */
-
-void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
-                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
-                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32G0xx_LL_UTILS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c

@@ -1,369 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_dma.c
-  * @author  MCD Application Team
-  * @brief   DMA LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_dma.h"
-#include "stm32g0xx_ll_bus.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup DMA_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
-                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
-                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
-
-#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
-                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
-
-#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
-                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
-
-#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
-                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
-
-#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
-                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
-                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
-
-#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
-                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
-                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
-
-#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
-
-#define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= LL_DMAMUX_MAX_REQ)
-
-#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
-
-#if defined(DMA2)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
-                                                            (((CHANNEL) == LL_DMA_CHANNEL_1) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_5) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_6) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
-                                                            (((INSTANCE) == DMA2) && \
-                                                            (((CHANNEL) == LL_DMA_CHANNEL_1) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_5))))
-#else /* DMA1 */
-#if   defined(DMA1_Channel7)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
-                                                            (((CHANNEL) == LL_DMA_CHANNEL_1) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_5) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_6) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
-                                                            (((CHANNEL) == LL_DMA_CHANNEL_1) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
-                                                             ((CHANNEL) == LL_DMA_CHANNEL_5))))
-#endif /* DMA1_Channel8 */
-#endif /* DMA2 */
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the DMA registers to their default reset values.
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  *         @arg @ref LL_DMA_CHANNEL_ALL
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DMA registers are de-initialized
-  *          - ERROR: DMA registers are not de-initialized
-  */
-ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the DMA Instance DMAx and Channel parameters*/
-  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
-
-  if (Channel == LL_DMA_CHANNEL_ALL)
-  {
-    if (DMAx == DMA1)
-    {
-      /* Force reset of DMA clock */
-      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
-
-      /* Release reset of DMA clock */
-      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
-    }
-#if defined(DMA2)
-    else if (DMAx == DMA2)
-    {
-      /* Force reset of DMA clock */
-      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
-
-      /* Release reset of DMA clock */
-      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
-    }
-#endif /* DMA2 */
-    else
-    {
-      status = ERROR;
-    }
-  }
-  else
-  {
-    DMA_Channel_TypeDef *tmp;
-
-    tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
-
-    /* Disable the selected DMAx_Channely */
-    CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
-
-    /* Reset DMAx_Channely control register */
-    WRITE_REG(tmp->CCR, 0U);
-
-    /* Reset DMAx_Channely remaining bytes register */
-    WRITE_REG(tmp->CNDTR, 0U);
-
-    /* Reset DMAx_Channely peripheral address register */
-    WRITE_REG(tmp->CPAR, 0U);
-
-    /* Reset DMAx_Channely memory address register */
-    WRITE_REG(tmp->CMAR, 0U);
-
-    /* Reset Request register field for DMAx Channel */
-    LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
-
-    if (Channel == LL_DMA_CHANNEL_1)
-    {
-      /* Reset interrupt pending bits for DMAx Channel1 */
-      LL_DMA_ClearFlag_GI1(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_2)
-    {
-      /* Reset interrupt pending bits for DMAx Channel2 */
-      LL_DMA_ClearFlag_GI2(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_3)
-    {
-      /* Reset interrupt pending bits for DMAx Channel3 */
-      LL_DMA_ClearFlag_GI3(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_4)
-    {
-      /* Reset interrupt pending bits for DMAx Channel4 */
-      LL_DMA_ClearFlag_GI4(DMAx);
-    }
-    else if (Channel == LL_DMA_CHANNEL_5)
-    {
-      /* Reset interrupt pending bits for DMAx Channel5 */
-      LL_DMA_ClearFlag_GI5(DMAx);
-    }
-#if defined(DMA1_Channel6)
-    else if (Channel == LL_DMA_CHANNEL_6)
-    {
-      /* Reset interrupt pending bits for DMAx Channel6 */
-      LL_DMA_ClearFlag_GI6(DMAx);
-    }
-#endif /* DMA1_Channel6 */
-#if defined(DMA1_Channel7)
-    else if (Channel == LL_DMA_CHANNEL_7)
-    {
-      /* Reset interrupt pending bits for DMAx Channel7 */
-      LL_DMA_ClearFlag_GI7(DMAx);
-    }
-#endif /* DMA1_Channel7 */
-    else
-    {
-      status = ERROR;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
-  * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
-  *         @arg @ref __LL_DMA_GET_INSTANCE
-  *         @arg @ref __LL_DMA_GET_CHANNEL
-  * @param  DMAx DMAx Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: DMA registers are initialized
-  *          - ERROR: Not applicable
-  */
-ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
-{
-  /* Check the DMA Instance DMAx and Channel parameters*/
-  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
-  /* Check the DMA parameters from DMA_InitStruct */
-  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
-  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
-  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
-  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
-  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
-  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
-  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
-  assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
-  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
-
-  /*---------------------------- DMAx CCR Configuration ------------------------
-   * Configure DMAx_Channely: data transfer direction, data transfer mode,
-   *                          peripheral and memory increment mode,
-   *                          data size alignment and  priority level with parameters :
-   * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
-   * - Mode:           DMA_CCR_CIRC bit
-   * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
-   * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
-   * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
-   * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
-   * - Priority:               DMA_CCR_PL[1:0] bits
-   */
-  LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
-                        DMA_InitStruct->Mode                   | \
-                        DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
-                        DMA_InitStruct->MemoryOrM2MDstIncMode  | \
-                        DMA_InitStruct->PeriphOrM2MSrcDataSize | \
-                        DMA_InitStruct->MemoryOrM2MDstDataSize | \
-                        DMA_InitStruct->Priority);
-
-  /*-------------------------- DMAx CMAR Configuration -------------------------
-   * Configure the memory or destination base address with parameter :
-   * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
-   */
-  LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
-
-  /*-------------------------- DMAx CPAR Configuration -------------------------
-   * Configure the peripheral or source base address with parameter :
-   * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
-   */
-  LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
-
-  /*--------------------------- DMAx CNDTR Configuration -----------------------
-   * Configure the peripheral base address with parameter :
-   * - NbData: DMA_CNDTR_NDT[15:0] bits
-   */
-  LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
-
-  /*--------------------------- DMAMUXx CCR Configuration ----------------------
-   * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
-   * - PeriphRequest: DMA_CxCR[7:0] bits
-   */
-  LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
-  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
-  * @retval None
-  */
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
-{
-  /* Set DMA_InitStruct fields to default values */
-  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
-  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
-  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
-  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
-  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
-  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
-  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
-  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
-  DMA_InitStruct->NbData                 = 0x00000000U;
-  DMA_InitStruct->PeriphRequest          = LL_DMAMUX_REQ_MEM2MEM;
-  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMA1 || DMA2 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_exti.c

@@ -1,295 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_exti.c
-  * @author  MCD Application Team
-  * @brief   EXTI LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_exti.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Private_Macros
-  * @{
-  */
-
-#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
-                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
-                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
-
-
-#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
-                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
-                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
-                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup EXTI_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the EXTI registers to their default reset values.
-  * @retval An ErrorStatus enumeration value:
-  *          - 0x00: EXTI registers are de-initialized
-  */
-uint32_t LL_EXTI_DeInit(void)
-{
-  /* Interrupt mask register set to default reset values */
-  LL_EXTI_WriteReg(IMR1,   0xFFF80000U);
-  /* Event mask register set to default reset values */
-  LL_EXTI_WriteReg(EMR1,   0x00000000U);
-  /* Rising Trigger selection register set to default reset values */
-  LL_EXTI_WriteReg(RTSR1,  0x00000000U);
-  /* Falling Trigger selection register set to default reset values */
-  LL_EXTI_WriteReg(FTSR1,  0x00000000U);
-  /* Software interrupt event register set to default reset values */
-  LL_EXTI_WriteReg(SWIER1, 0x00000000U);
-  /* Pending register set to default reset values */
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
-  LL_EXTI_WriteReg(RPR1,    0x0017FFFFU);
-  LL_EXTI_WriteReg(FPR1,    0x0017FFFFU);
-#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G061xx) || defined(STM32G051xx)
-  LL_EXTI_WriteReg(RPR1,    0x0007FFFFU);
-  LL_EXTI_WriteReg(FPR1,    0x0007FFFFU);
-#elif defined(STM32G041xx) || defined(STM32G031xx)
-  LL_EXTI_WriteReg(RPR1,    0x0001FFFFU);
-  LL_EXTI_WriteReg(FPR1,    0x0001FFFFU);
-#elif defined(STM32G0B0xx) || defined(STM32G070xx) || defined(STM32G050xx) || defined(STM32G030xx)
-  LL_EXTI_WriteReg(RPR1,    0x0000FFFFU);
-  LL_EXTI_WriteReg(FPR1,    0x0000FFFFU);
-#endif /* STM32G0C1xx || STM32G0B1xx */
-
-#if defined(STM32G081xx) || defined(STM32G071xx)
-  /* Interrupt mask register 2 set to default reset values */
-  LL_EXTI_WriteReg(IMR2, 0x00000003U);
-  /* Event mask register 2 set to default reset values */
-  LL_EXTI_WriteReg(EMR2, 0x00000000U);
-#elif defined(STM32G0C1xx) || defined(STM32G0B1xx)
-  /* Interrupt mask register 2 set to default reset values */
-  LL_EXTI_WriteReg(IMR2, 0x0000001FU);
-  /* Event mask register 2 set to default reset values */
-  LL_EXTI_WriteReg(EMR2, 0x00000000U);
-  /* Rising Trigger selection register set to default reset values */
-  LL_EXTI_WriteReg(RTSR2, 0x00000000U);
-  /* Falling Trigger selection register set to default reset values */
-  LL_EXTI_WriteReg(FTSR2, 0x00000000U);
-  /* Software interrupt event register set to default reset values */
-  LL_EXTI_WriteReg(SWIER2, 0x00000000U);
-  /* Pending register set to default reset values */
-  LL_EXTI_WriteReg(RPR2, 0x00000004U);
-  LL_EXTI_WriteReg(FPR2, 0x00000004U);
-#elif defined(STM32G0B0xx)
-  /* Interrupt mask register 2 set to default reset values */
-  LL_EXTI_WriteReg(IMR2, 0x00000010U);
-  /* Event mask register 2 set to default reset values */
-  LL_EXTI_WriteReg(EMR2, 0x00000000U);
-#endif /* STM32G081xx || STM32G071xx */
-
-  return 0x00u;
-}
-
-/**
-  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
-  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
-  * @retval An ErrorStatus enumeration value:
-  *          - 0x00: EXTI registers are initialized
-  *          - any other value : wrong configuration
-  */
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
-  uint32_t status = 0x00u;
-
-  /* Check the parameters */
-  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-  assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
-  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
-
-  /* ENABLE LineCommand */
-  if (EXTI_InitStruct->LineCommand != DISABLE)
-  {
-    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
-
-    /* Configure EXTI Lines in range from 0 to 31 */
-    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
-    {
-      switch (EXTI_InitStruct->Mode)
-      {
-        case LL_EXTI_MODE_IT:
-          /* First Disable Event on provided Lines */
-          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
-          /* Then Enable IT on provided Lines */
-          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
-          break;
-        case LL_EXTI_MODE_EVENT:
-          /* First Disable IT on provided Lines */
-          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
-          /* Then Enable Event on provided Lines */
-          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
-          break;
-        case LL_EXTI_MODE_IT_EVENT:
-          /* Directly Enable IT & Event on provided Lines */
-          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
-          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
-          break;
-        default:
-          status = 0x01u;
-          break;
-      }
-      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
-      {
-        switch (EXTI_InitStruct->Trigger)
-        {
-          case LL_EXTI_TRIGGER_RISING:
-            /* First Disable Falling Trigger on provided Lines */
-            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            /* Then Enable Rising Trigger on provided Lines */
-            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            break;
-          case LL_EXTI_TRIGGER_FALLING:
-            /* First Disable Rising Trigger on provided Lines */
-            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            /* Then Enable Falling Trigger on provided Lines */
-            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            break;
-          case LL_EXTI_TRIGGER_RISING_FALLING:
-            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
-            break;
-          default:
-            status |= 0x02u;
-            break;
-        }
-      }
-    }
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-    /* Configure EXTI Lines in range from 32 to 63 */
-    if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
-    {
-      switch (EXTI_InitStruct->Mode)
-      {
-        case LL_EXTI_MODE_IT:
-          /* First Disable Event on provided Lines */
-          LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
-          /* Then Enable IT on provided Lines */
-          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
-          break;
-        case LL_EXTI_MODE_EVENT:
-          /* First Disable IT on provided Lines */
-          LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
-          /* Then Enable Event on provided Lines */
-          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
-          break;
-        case LL_EXTI_MODE_IT_EVENT:
-          /* Directly Enable IT & Event on provided Lines */
-          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
-          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
-          break;
-        default:
-          status |= 0x04u;
-          break;
-      }
-    }
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-  }
-  /* DISABLE LineCommand */
-  else
-  {
-    /* De-configure EXTI Lines in range from 0 to 31 */
-    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
-    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-    /* De-configure EXTI Lines in range from 32 to 63 */
-    LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
-    LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
-  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
-  * @retval None
-  */
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
-  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
-#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-  EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
-#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-  EXTI_InitStruct->LineCommand    = DISABLE;
-  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
-  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (EXTI) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c

@@ -1,281 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_gpio.c
-  * @author  MCD Application Team
-  * @brief   GPIO LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_gpio.h"
-#include "stm32g0xx_ll_bus.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
-
-/** @addtogroup GPIO_LL
-  * @{
-  */
-/** MISRA C:2012 deviation rule has been granted for following rules:
-  * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
-  * range of the shift operator in following API :
-  * LL_GPIO_Init
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
-
-#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
-                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
-                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
-                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
-
-#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
-                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
-
-#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
-                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
-
-#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
-                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
-                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
-
-#if defined(GPIOE)
-#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_10 ))
-#else
-#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
-                                            ((__VALUE__) == LL_GPIO_AF_7 ))
-#endif /* GPIOE */
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize GPIO registers (Registers restored to their default values).
-  * @param  GPIOx GPIO Port
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: GPIO registers are de-initialized
-  *          - ERROR:   Wrong GPIO Port
-  */
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
-  /* Force and Release reset on clock of GPIOx Port */
-  if (GPIOx == GPIOA)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA);
-  }
-  else if (GPIOx == GPIOB)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB);
-  }
-  else if (GPIOx == GPIOC)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOC);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOC);
-  }
-#if defined(GPIOD)
-  else if (GPIOx == GPIOD)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOD);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOD);
-  }
-#endif /* GPIOD */
-#if defined(GPIOE)
-  else if (GPIOx == GPIOE)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOE);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOE);
-  }
-#endif /* GPIOE */
-#if defined(GPIOF)
-  else if (GPIOx == GPIOF)
-  {
-    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOF);
-    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOF);
-  }
-#endif /* GPIOF */
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
-  * @param  GPIOx GPIO Port
-  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
-  *         that contains the configuration information for the specified GPIO peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
-  *          - ERROR:   Not applicable
-  */
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
-  uint32_t pinpos;
-  uint32_t currentpin;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
-  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
-  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
-
-  /* ------------------------- Configure the port pins ---------------- */
-  /* Initialize  pinpos on first pin set */
-  pinpos = 0;
-
-  /* Configure the port pins */
-  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
-  {
-    /* Get current io position */
-    currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
-
-    if (currentpin != 0x00u)
-    {
-      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
-      {
-        /* Check Speed mode parameters */
-        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
-
-        /* Speed mode configuration */
-        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
-
-        /* Check Output mode parameters */
-        assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
-        /* Output mode configuration*/
-        LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
-      }
-
-      /* Pull-up Pull down resistor configuration*/
-      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
-
-      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
-      {
-        /* Check Alternate parameter */
-        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
-
-        /* Speed mode configuration */
-        if (currentpin < LL_GPIO_PIN_8)
-        {
-          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
-        }
-        else
-        {
-          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
-        }
-      }
-
-      /* Pin Mode configuration */
-      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-    }
-    pinpos++;
-  }
-
-  return (SUCCESS);
-}
-
-/**
-  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
-  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
-  *                          whose fields will be set to default values.
-  * @retval None
-  */
-
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
-  /* Reset GPIO init structure parameters values */
-  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
-  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
-  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
-  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
-  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
-  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_i2c.c

@@ -1,237 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_i2c.c
-  * @author  MCD Application Team
-  * @brief   I2C LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_i2c.h"
-#include "stm32g0xx_ll_bus.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (I2C1) || defined (I2C2) || defined (I2C3)
-
-/** @defgroup I2C_LL I2C
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup I2C_LL_Private_Macros
-  * @{
-  */
-
-#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
-                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
-                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
-                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
-
-#define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
-                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
-
-#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
-
-#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
-
-#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
-                                                 ((__VALUE__) == LL_I2C_NACK))
-
-#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
-                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the I2C registers to their default reset values.
-  * @param  I2Cx I2C Instance.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: I2C registers are de-initialized
-  *          - ERROR: I2C registers are not de-initialized
-  */
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the I2C Instance I2Cx */
-  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
-  if (I2Cx == I2C1)
-  {
-    /* Force reset of I2C clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
-
-    /* Release reset of I2C clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
-  }
-  else if (I2Cx == I2C2)
-  {
-    /* Force reset of I2C clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
-
-    /* Release reset of I2C clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
-
-  }
-#if defined(I2C3)
-  else if (I2Cx == I2C3)
-  {
-    /* Force reset of I2C clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
-
-    /* Release reset of I2C clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
-  }
-#endif /* I2C3 */
-  else
-  {
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
-  * @param  I2Cx I2C Instance.
-  * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: I2C registers are initialized
-  *          - ERROR: Not applicable
-  */
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
-{
-  /* Check the I2C Instance I2Cx */
-  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
-
-  /* Check the I2C parameters from I2C_InitStruct */
-  assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
-  assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
-  assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
-  assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
-  assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
-  assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
-
-  /* Disable the selected I2Cx Peripheral */
-  LL_I2C_Disable(I2Cx);
-
-  /*---------------------------- I2Cx CR1 Configuration ------------------------
-   * Configure the analog and digital noise filters with parameters :
-   * - AnalogFilter: I2C_CR1_ANFOFF bit
-   * - DigitalFilter: I2C_CR1_DNF[3:0] bits
-   */
-  LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
-
-  /*---------------------------- I2Cx TIMINGR Configuration --------------------
-   * Configure the SDA setup, hold time and the SCL high, low period with parameter :
-   * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
-   *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
-   */
-  LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
-
-  /* Enable the selected I2Cx Peripheral */
-  LL_I2C_Enable(I2Cx);
-
-  /*---------------------------- I2Cx OAR1 Configuration -----------------------
-   * Disable, Configure and Enable I2Cx device own address 1 with parameters :
-   * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
-   * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
-   */
-  LL_I2C_DisableOwnAddress1(I2Cx);
-  LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
-
-  /* OwnAdress1 == 0 is reserved for General Call address */
-  if (I2C_InitStruct->OwnAddress1 != 0U)
-  {
-    LL_I2C_EnableOwnAddress1(I2Cx);
-  }
-
-  /*---------------------------- I2Cx MODE Configuration -----------------------
-  * Configure I2Cx peripheral mode with parameter :
-   * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
-   */
-  LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
-
-  /*---------------------------- I2Cx CR2 Configuration ------------------------
-   * Configure the ACKnowledge or Non ACKnowledge condition
-   * after the address receive match code or next received byte with parameter :
-   * - TypeAcknowledge: I2C_CR2_NACK bit
-   */
-  LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
-  * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
-  * @retval None
-  */
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
-{
-  /* Set I2C_InitStruct fields to default values */
-  I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
-  I2C_InitStruct->Timing          = 0U;
-  I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
-  I2C_InitStruct->DigitalFilter   = 0U;
-  I2C_InitStruct->OwnAddress1     = 0U;
-  I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
-  I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* I2C1 || I2C2 || I2C3 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_pwr.c

@@ -1,85 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_pwr.c
-  * @author  MCD Application Team
-  * @brief   PWR LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_pwr.h"
-#include "stm32g0xx_ll_bus.h"
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup PWR_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the PWR registers to their default reset values.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: PWR registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_PWR_DeInit(void)
-{
-  /* Force reset of PWR clock */
-  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
-
-  /* Release reset of PWR clock */
-  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
-
-  return SUCCESS;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* defined(PWR) */
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c

@@ -1,1358 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_rcc.c
-  * @author  MCD Application Team
-  * @brief   RCC LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_rcc.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @addtogroup RCC_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_LL_Private_Macros
-  * @{
-  */
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
-                                               || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
-                                               || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
-#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
-                                               || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
-#else
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  ((__VALUE__) == LL_RCC_USART1_CLKSOURCE)
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-#if defined(LPUART1) && defined(LPUART2)
-#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) \
-                                                || ((__VALUE__) == LL_RCC_LPUART2_CLKSOURCE))
-#elif defined(LPUART1)
-#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__)   ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)
-#endif /* LPUART1 && LPUART2 */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
-                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
-#else
-#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)   ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-#if defined(LPTIM1) || defined(LPTIM2)
-#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
-                                               || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
-#endif /* LPTIM1 || LPTIM2 */
-
-#if defined(RNG)
-#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
-#endif /* RNG */
-
-#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
-                                             || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
-#else
-#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-#if defined(CEC)
-#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
-#endif /* CEC */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-#if defined(FDCAN1) || defined(FDCAN2)
-#define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
-#endif /* FDCAN1 || FDCAN2 */
-
-#if defined(RCC_CCIPR_TIM1SEL) && defined(RCC_CCIPR_TIM15SEL)
-#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
-                                               || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE))
-#elif defined(RCC_CCIPR_TIM1SEL)
-#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE))
-#endif /* RCC_CCIPR_TIM1SEL */
-
-
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_LL_Private_Functions RCC Private functions
-  * @{
-  */
-static uint32_t RCC_GetSystemClockFreq(void);
-static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-static uint32_t RCC_PLL_GetFreqDomain_ADC(void);
-static uint32_t RCC_PLL_GetFreqDomain_I2S1(void);
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-static uint32_t RCC_PLL_GetFreqDomain_I2S2(void);
-static uint32_t RCC_PLL_GetFreqDomain_USB(void);
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-#if defined(FDCAN1) || defined(FDCAN2)
-static uint32_t RCC_PLL_GetFreqDomain_FDCAN(void);
-#endif /* FDCAN1 || FDCAN2 */
-#if defined(RNG)
-static uint32_t RCC_PLL_GetFreqDomain_RNG(void);
-#endif /* RNG */
-#if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL)
-static uint32_t RCC_PLL_GetFreqDomain_TIM1(void);
-#endif /* RCC_PLLQ_SUPPORT && RCC_CCIPR_TIM1SEL */
-#if defined(RCC_CCIPR_TIM15SEL)
-static uint32_t RCC_PLL_GetFreqDomain_TIM15(void);
-#endif /* RCC_CCIPR_TIM15SEL */
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  Reset the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *         - HSI ON and used as system clock source
-  *         - HSE and PLL OFF
-  *         - AHB and APB1 prescaler set to 1.
-  *         - CSS, MCO OFF
-  *         - All interrupts disabled
-  * @note   This function does not modify the configuration of the
-  *         - Peripheral clocks
-  *         - LSI, LSE and RTC clocks
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RCC registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_RCC_DeInit(void)
-{
-  /* Set HSION bit and wait for HSI READY bit */
-  LL_RCC_HSI_Enable();
-  while (LL_RCC_HSI_IsReady() != 1U)
-  {}
-
-  /* Set HSITRIM bits to reset value*/
-  LL_RCC_HSI_SetCalibTrimming(0x40U);
-
-  /* Reset CFGR register */
-  LL_RCC_WriteReg(CFGR, 0x00000000U);
-
-  /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */
-  LL_RCC_WriteReg(CR, RCC_CR_HSION);
-  while (LL_RCC_HSE_IsReady() != 0U)
-  {}
-  LL_RCC_WriteReg(CR, RCC_CR_HSION);
-
-  /* Wait for PLL READY bit to be reset */
-  while (LL_RCC_PLL_IsReady() != 0U)
-  {}
-
-  /* Reset PLLCFGR register */
-  LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
-
-  /* Disable all interrupts */
-  LL_RCC_WriteReg(CIER, 0x00000000U);
-
-  /* Clear all interrupts flags */
-  LL_RCC_WriteReg(CICR, 0xFFFFFFFFU);
-
-  return SUCCESS;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_LL_EF_Get_Freq
-  * @brief  Return the frequencies of different on chip clocks;  System, AHB and APB1 buses clocks
-  *         and different peripheral clocks available on the device.
-  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE divided by HSI division factor(**)
-  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
-  * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
-  *         or HSI_VALUE(**) multiplied/divided by the PLL factors.
-  * @note   (**) HSI_VALUE is a constant defined in this file (default value
-  *              16 MHz) but the real value may vary depending on the variations
-  *              in voltage and temperature.
-  * @note   (***) HSE_VALUE is a constant defined in this file (default value
-  *               8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *               frequency of the crystal used. Otherwise, this function may
-  *               have wrong result.
-  * @note   The result of this function could be incorrect when using fractional
-  *         value for HSE crystal.
-  * @note   This function can be used by the user application to compute the
-  *         baud-rate for the communication peripherals or configure other parameters.
-  * @{
-  */
-
-/**
-  * @brief  Return the frequencies of different on chip clocks;  System, AHB and APB1 buses clocks
-  * @note   Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function
-  *         must be called to update structure fields. Otherwise, any
-  *         configuration based on this function will be incorrect.
-  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
-  * @retval None
-  */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
-{
-  /* Get SYSCLK frequency */
-  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
-
-  /* HCLK clock frequency */
-  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
-
-  /* PCLK1 clock frequency */
-  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
-}
-
-/**
-  * @brief  Return USARTx clock frequency
-  * @param  USARTxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USART1_CLKSOURCE
-  *         @arg @ref LL_RCC_USART2_CLKSOURCE
-  *         @arg @ref LL_RCC_USART3_CLKSOURCE
-  * @retval USART clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
-  */
-uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
-{
-  uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
-
-  if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
-  {
-    /* USART1CLK clock frequency */
-    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
-    {
-      case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
-        usart_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() == 1U)
-        {
-          usart_frequency = HSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() == 1U)
-        {
-          usart_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_USART1_CLKSOURCE_PCLK1:  /* USART1 Clock is PCLK1 */
-      default:
-        usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#if defined(RCC_CCIPR_USART2SEL)
-  else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
-  {
-    /* USART2CLK clock frequency */
-    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
-    {
-      case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
-        usart_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() == 1U)
-        {
-          usart_frequency = HSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() == 1U)
-        {
-          usart_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
-      default:
-        usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#endif /* RCC_CCIPR_USART2SEL */
-#if defined(RCC_CCIPR_USART3SEL)
-  else if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
-  {
-    /* USART3CLK clock frequency */
-    switch (LL_RCC_GetUSARTClockSource(USARTxSource))
-    {
-      case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
-        usart_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() == 1U)
-        {
-          usart_frequency = HSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() == 1U)
-        {
-          usart_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */
-      default:
-        usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#endif /* RCC_CCIPR_USART3SEL */
-  else
-  {
-    /* nothing to do */
-  }
-  return usart_frequency;
-}
-
-/**
-  * @brief  Return I2Cx clock frequency
-  * @param  I2CxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2C1_CLKSOURCE
-  * @retval I2C clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
-  */
-uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
-{
-  uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
-
-  if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
-  {
-    /* I2C1 CLK clock frequency */
-    switch (LL_RCC_GetI2CClockSource(I2CxSource))
-    {
-      case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
-        i2c_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() == 1U)
-        {
-          i2c_frequency = HSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
-      default:
-        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#if defined(RCC_CCIPR_I2C2SEL)
-  else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
-  {
-    /* I2C2 CLK clock frequency */
-    switch (LL_RCC_GetI2CClockSource(I2CxSource))
-    {
-      case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
-        i2c_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() == 1U)
-        {
-          i2c_frequency = HSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_I2C2_CLKSOURCE_PCLK1:  /* I2C2 Clock is PCLK1 */
-      default:
-        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#endif /* RCC_CCIPR_I2C2SEL */
-  else
-  {
-    /* nothing to do */
-  }
-
-  return i2c_frequency;
-}
-
-/**
-  * @brief  Return I2Sx clock frequency
-  * @param  I2SxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE
-  * @retval I2S clock frequency (in Hz)
-  *         @arg @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
-  */
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
-{
-  uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
-
-  if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
-  {
-    /* I2S1 CLK clock frequency */
-    switch (LL_RCC_GetI2SClockSource(I2SxSource))
-    {
-      case LL_RCC_I2S1_CLKSOURCE_HSI:    /* I2S1 Clock is HSI */
-        i2s_frequency = HSI_VALUE;
-        break;
-
-      case LL_RCC_I2S1_CLKSOURCE_PLL:    /* I2S1 Clock is PLL"P" */
-        if (LL_RCC_PLL_IsReady() == 1U)
-        {
-          i2s_frequency = RCC_PLL_GetFreqDomain_I2S1();
-        }
-        break;
-
-
-      case LL_RCC_I2S1_CLKSOURCE_PIN:          /* I2S1 Clock is External clock */
-        i2s_frequency = EXTERNAL_CLOCK_VALUE;
-        break;
-
-      case LL_RCC_I2S1_CLKSOURCE_SYSCLK: /* I2S1 Clock is System Clock */
-      default:
-        i2s_frequency = RCC_GetSystemClockFreq();
-        break;
-    }
-  }
-#if defined(RCC_CCIPR2_I2S2SEL)
-  else if (I2SxSource == LL_RCC_I2S2_CLKSOURCE)
-  {
-    /* I2S2 CLK clock frequency */
-    switch (LL_RCC_GetI2SClockSource(I2SxSource))
-    {
-      case LL_RCC_I2S2_CLKSOURCE_HSI:    /* I2S2 Clock is HSI */
-        i2s_frequency = HSI_VALUE;
-        break;
-
-      case LL_RCC_I2S2_CLKSOURCE_PLL:    /* I2S2 Clock is PLL"P" */
-        if (LL_RCC_PLL_IsReady() == 1U)
-        {
-          i2s_frequency = RCC_PLL_GetFreqDomain_I2S2();
-        }
-        break;
-
-      case LL_RCC_I2S2_CLKSOURCE_PIN:          /* I2S2 Clock is External clock */
-        i2s_frequency = EXTERNAL_CLOCK_VALUE;
-        break;
-
-      case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /* I2S2 Clock is System Clock */
-      default:
-        i2s_frequency = RCC_GetSystemClockFreq();
-        break;
-    }
-  }
-#endif /* RCC_CCIPR2_I2S2SEL */
-  else
-  {
-  }
-  return i2s_frequency;
-}
-
-#if defined(LPUART1) || defined(LPUART2)
-/**
-  * @brief  Return LPUARTx clock frequency
-  * @param  LPUARTxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
-  *         @arg @ref LL_RCC_LPUART2_CLKSOURCE (*)
-  * @retval LPUART clock frequency (in Hz)
-  *         @arg @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
-  * (*) feature not available on all devices
-  */
-uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
-{
-  uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
-
-  if (LPUARTxSource == LL_RCC_LPUART1_CLKSOURCE)
-  {
-    /* LPUART1CLK clock frequency */
-    switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
-    {
-      case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
-        lpuart_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() == 1U)
-        {
-          lpuart_frequency = HSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() == 1U)
-        {
-          lpuart_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */
-      default:
-        lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#if defined(LPUART2)
-  else if (LPUARTxSource == LL_RCC_LPUART2_CLKSOURCE)
-  {
-    /* LPUART2CLK clock frequency */
-    switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
-    {
-      case LL_RCC_LPUART2_CLKSOURCE_SYSCLK: /* LPUART2 Clock is System Clock */
-        lpuart_frequency = RCC_GetSystemClockFreq();
-        break;
-
-      case LL_RCC_LPUART2_CLKSOURCE_HSI:    /* LPUART2 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() == 1U)
-        {
-          lpuart_frequency = HSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPUART2_CLKSOURCE_LSE:    /* LPUART2 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() == 1U)
-        {
-          lpuart_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPUART2_CLKSOURCE_PCLK1:  /* LPUART2 Clock is PCLK1 */
-      default:
-        lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#endif /* LPUART2 */
-  else
-  {
-  }
-
-  return lpuart_frequency;
-}
-#endif /* LPUART1 */
-
-#if defined(LPTIM1) && defined(LPTIM2)
-/**
-  * @brief  Return LPTIMx clock frequency
-  * @param  LPTIMxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
-  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
-  * @retval LPTIM clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
-  */
-uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
-{
-  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
-
-  if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
-  {
-    /* LPTIM1CLK clock frequency */
-    switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
-    {
-      case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
-        if (LL_RCC_LSI_IsReady() == 1U)
-        {
-          lptim_frequency = LSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() == 1U)
-        {
-          lptim_frequency = HSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() == 1U)
-        {
-          lptim_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
-      default:
-        lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-  else
-  {
-    /* LPTIM2CLK clock frequency */
-    switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
-    {
-      case LL_RCC_LPTIM2_CLKSOURCE_LSI:    /* LPTIM2 Clock is LSI Osc. */
-        if (LL_RCC_LSI_IsReady() == 1U)
-        {
-          lptim_frequency = LSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPTIM2_CLKSOURCE_HSI:    /* LPTIM2 Clock is HSI Osc. */
-        if (LL_RCC_HSI_IsReady() == 1U)
-        {
-          lptim_frequency = HSI_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPTIM2_CLKSOURCE_LSE:    /* LPTIM2 Clock is LSE Osc. */
-        if (LL_RCC_LSE_IsReady() == 1U)
-        {
-          lptim_frequency = LSE_VALUE;
-        }
-        break;
-
-      case LL_RCC_LPTIM2_CLKSOURCE_PCLK1:  /* LPTIM2 Clock is PCLK1 */
-      default:
-        lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-
-  return lptim_frequency;
-}
-#endif /* LPTIM1 && LPTIM2 */
-
-#if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
-/**
-  * @brief  Return TIMx clock frequency
-  * @param  TIMxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_TIM1_CLKSOURCE
-  * @if defined(STM32G081xx)
-  *         @arg @ref LL_RCC_TIM15_CLKSOURCE
-  * @endif
-  * @retval TIMx clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
-  */
-uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
-{
-  uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
-
-  if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
-  {
-    /* TIM1CLK clock frequency */
-    switch (LL_RCC_GetTIMClockSource(TIMxSource))
-    {
-      case LL_RCC_TIM1_CLKSOURCE_PLL:    /* TIM1 Clock is PLLQ */
-        if (LL_RCC_PLL_IsReady() == 1U)
-        {
-          tim_frequency = RCC_PLL_GetFreqDomain_TIM1();
-        }
-        break;
-
-      case LL_RCC_TIM1_CLKSOURCE_PCLK1:  /* TIM1 Clock is PCLK1 */
-      default:
-        tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-        break;
-    }
-  }
-#if defined(TIM15)
-  else
-  {
-    if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
-    {
-      /* TIM15CLK clock frequency */
-      switch (LL_RCC_GetTIMClockSource(TIMxSource))
-      {
-        case LL_RCC_TIM15_CLKSOURCE_PLL:    /* TIM1 Clock is PLLQ */
-          if (LL_RCC_PLL_IsReady() == 1U)
-          {
-            tim_frequency = RCC_PLL_GetFreqDomain_TIM15();
-          }
-          break;
-
-        case LL_RCC_TIM15_CLKSOURCE_PCLK1:  /* TIM15 Clock is PCLK1 */
-        default:
-          tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-          break;
-      }
-    }
-  }
-#endif /* TIM15 */
-  return tim_frequency;
-}
-#endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */
-
-
-#if defined(RNG)
-/**
-  * @brief  Return RNGx clock frequency
-  * @param  RNGxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE
-  * @retval RNG clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
-  */
-uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
-{
-  uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-  uint32_t rngdiv;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
-
-  /* RNGCLK clock frequency */
-  switch (LL_RCC_GetRNGClockSource(RNGxSource))
-  {
-    case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */
-      if (LL_RCC_PLL_IsReady() == 1U)
-      {
-        rng_frequency = RCC_PLL_GetFreqDomain_RNG();
-        rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos));
-        rng_frequency = (rng_frequency / rngdiv);
-      }
-      break;
-
-    case LL_RCC_RNG_CLKSOURCE_HSI_DIV8:      /* HSI clock divided by 8 used as RNG clock source */
-      rng_frequency = HSI_VALUE / 8U;
-      rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos));
-      rng_frequency = (rng_frequency / rngdiv);
-      break;
-    case LL_RCC_RNG_CLKSOURCE_SYSCLK:        /* SYSCLK clock used as RNG clock source */
-      rng_frequency = RCC_GetSystemClockFreq();
-      rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos));
-      rng_frequency = (rng_frequency / rngdiv);
-      break;
-
-    case LL_RCC_RNG_CLKSOURCE_NONE:          /* No clock used as RNG clock source */
-    default:
-      rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
-      break;
-
-  }
-
-  return rng_frequency;
-}
-#endif /* RNG */
-
-#if defined(CEC)
-/**
-  * @brief  Return CEC clock frequency
-  * @param  CECxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE
-  * @retval CEC clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
-  */
-uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
-{
-  uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
-
-  /* CECCLK clock frequency */
-  switch (LL_RCC_GetCECClockSource(CECxSource))
-  {
-    case LL_RCC_CEC_CLKSOURCE_LSE:           /* CEC Clock is LSE Osc. */
-      if (LL_RCC_LSE_IsReady() == 1U)
-      {
-        cec_frequency = LSE_VALUE;
-      }
-      break;
-
-    case LL_RCC_CEC_CLKSOURCE_HSI_DIV488:    /* CEC Clock is HSI Osc. */
-    default:
-      if (LL_RCC_HSI_IsReady() == 1U)
-      {
-        cec_frequency = (HSI_VALUE / 488U);
-      }
-      break;
-  }
-
-  return cec_frequency;
-}
-#endif /* CEC */
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/**
-  * @brief  Return FDCANx clock frequency
-  * @param  FDCANxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
-  * @retval FDCANx clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
-  */
-uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
-{
-  uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
-
-  /* FDCANCLK clock frequency */
-  switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
-  {
-    case LL_RCC_FDCAN_CLKSOURCE_PLL:    /* FDCAN Clock is PLL "Q"  Osc. */
-      if (LL_RCC_PLL_IsReady() == 1U)
-      {
-        fdcan_frequency = RCC_PLL_GetFreqDomain_FDCAN();
-      }
-      break;
-
-    case LL_RCC_FDCAN_CLKSOURCE_HSE:    /* FDCAN Clock is HSE Osc. */
-      if (LL_RCC_HSE_IsReady() == 1U)
-      {
-        fdcan_frequency = HSE_VALUE;
-      }
-      break;
-
-    case LL_RCC_FDCAN_CLKSOURCE_PCLK1:  /* FDCAN Clock is PCLK1 */
-    default:
-      fdcan_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
-      break;
-  }
-
-  return fdcan_frequency;
-}
-#endif /* FDCAN1 || FDCAN2 */
-
-/**
-  * @brief  Return ADCx clock frequency
-  * @param  ADCxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_ADC_CLKSOURCE
-  * @retval ADC clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
-  */
-uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
-{
-  uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
-
-  /* ADCCLK clock frequency */
-  switch (LL_RCC_GetADCClockSource(ADCxSource))
-  {
-    case LL_RCC_ADC_CLKSOURCE_SYSCLK:        /* SYSCLK clock used as ADC clock source */
-      adc_frequency = RCC_GetSystemClockFreq();
-      break;
-    case LL_RCC_ADC_CLKSOURCE_HSI  :        /* HSI clock used as ADC clock source */
-      adc_frequency = HSI_VALUE;
-      break;
-
-    case LL_RCC_ADC_CLKSOURCE_PLL:         /* PLLP clock used as ADC clock source */
-      if (LL_RCC_PLL_IsReady() == 1U)
-      {
-        adc_frequency = RCC_PLL_GetFreqDomain_ADC();
-      }
-      break;
-    default:
-      adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
-      break;
-  }
-
-  return adc_frequency;
-}
-
-/**
-  * @brief  Return RTC clock frequency
-  * @retval RTC clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
-  */
-uint32_t LL_RCC_GetRTCClockFreq(void)
-{
-  uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* RTCCLK clock frequency */
-  switch (LL_RCC_GetRTCClockSource())
-  {
-    case LL_RCC_RTC_CLKSOURCE_LSE:       /* LSE clock used as RTC clock source */
-      if (LL_RCC_LSE_IsReady() == 1U)
-      {
-        rtc_frequency = LSE_VALUE;
-      }
-      break;
-
-    case LL_RCC_RTC_CLKSOURCE_LSI:       /* LSI clock used as RTC clock source */
-      if (LL_RCC_LSI_IsReady() == 1U)
-      {
-        rtc_frequency = LSI_VALUE;
-      }
-      break;
-
-    case LL_RCC_RTC_CLKSOURCE_HSE_DIV32:        /* HSE clock used as ADC clock source */
-      rtc_frequency = HSE_VALUE / 32U;
-      break;
-
-    case LL_RCC_RTC_CLKSOURCE_NONE:          /* No clock used as RTC clock source */
-    default:
-      rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
-      break;
-  }
-
-  return rtc_frequency;
-}
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Return USBx clock frequency
-  * @param  USBxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE
-  * @retval USB clock frequency (in Hz)
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
-  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
-  */
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
-{
-  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
-  /* Check parameter */
-  assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
-
-  /* USBCLK clock frequency */
-  switch (LL_RCC_GetUSBClockSource(USBxSource))
-  {
-#if defined(RCC_HSI48_SUPPORT)
-    case LL_RCC_USB_CLKSOURCE_HSI48:         /* HSI48 used as USB clock source */
-      if (LL_RCC_HSI48_IsReady() != 0U)
-      {
-        usb_frequency = HSI48_VALUE;
-      }
-      break;
-#endif /* RCC_HSI48_SUPPORT */
-
-    case LL_RCC_USB_CLKSOURCE_HSE:         /* HSE used as USB clock source */
-      if (LL_RCC_HSE_IsReady() != 0U)
-      {
-        usb_frequency = HSE_VALUE;
-      }
-      break;
-
-    case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
-      if (LL_RCC_PLL_IsReady() != 0U)
-      {
-        usb_frequency = RCC_PLL_GetFreqDomain_USB();
-      }
-      break;
-
-    default:
-      usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
-      break;
-  }
-
-  return usb_frequency;
-}
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx) */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_LL_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Return SYSTEM clock frequency
-  * @retval SYSTEM clock frequency (in Hz)
-  */
-static uint32_t RCC_GetSystemClockFreq(void)
-{
-  uint32_t frequency;
-  uint32_t hsidiv;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (LL_RCC_GetSysClkSource())
-  {
-    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
-      frequency = HSE_VALUE;
-      break;
-
-    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
-      frequency = RCC_PLL_GetFreqDomain_SYS();
-      break;
-
-    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
-    default:
-      hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
-      frequency = (HSI_VALUE / hsidiv);
-      break;
-  }
-
-  return frequency;
-}
-
-/**
-  * @brief  Return HCLK clock frequency
-  * @param  SYSCLK_Frequency SYSCLK clock frequency
-  * @retval HCLK clock frequency (in Hz)
-  */
-static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
-{
-  /* HCLK clock frequency */
-  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
-}
-
-/**
-  * @brief  Return PCLK1 clock frequency
-  * @param  HCLK_Frequency HCLK clock frequency
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
-{
-  /* PCLK1 clock frequency */
-  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
-}
-/**
-  * @brief  Return PLL clock frequency used for system domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
-{
-  uint32_t pllinputfreq;
-  uint32_t pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-     SYSCLK = PLL_VCO / PLLR
-  */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-      pllinputfreq = HSI_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
-                                   LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
-}
-/**
-  * @brief  Return PLL clock frequency used for ADC domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_ADC(void)
-{
-  uint32_t pllinputfreq;
-  uint32_t pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-     ADC Domain clock = PLL_VCO / PLLP
-  */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
-                                       LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
-}
-
-#if defined(FDCAN1) || defined(FDCAN2)
-/**
-  * @brief  Return PLL clock frequency used for FDCAN domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_FDCAN(void)
-{
-  uint32_t pllinputfreq;
-  uint32_t pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
-
-     FDCAN Domain clock = PLL_VCO / PLLQ
-  */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
-                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
-}
-#endif /* FDCAN1 || FDCAN2 */
-
-/**
-  * @brief  Return PLL clock frequency used for I2S1 domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_I2S1(void)
-{
-  uint32_t pllinputfreq;
-  uint32_t pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-     I2S1 Domain clock = PLL_VCO / PLLP
-  */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_I2S1_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
-                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
-}
-
-#if defined(RCC_CCIPR2_I2S2SEL)
-/**
-  * @brief  Return PLL clock frequency used for I2S2 domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_I2S2(void)
-{
-  uint32_t pllinputfreq;
-  uint32_t pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-     I2S2 Domain clock = PLL_VCO / PLLP
-  */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_I2S2_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
-                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
-}
-#endif /* RCC_CCIPR2_I2S2SEL */
-
-#if defined(RNG)
-/**
-  * @brief  Return PLL clock frequency used for RNG domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_RNG(void)
-{
-  uint32_t pllinputfreq;
-  uint32_t pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
-
-     RNG Domain clock = PLL_VCO / PLLQ
-  */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_RNG_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
-                                       LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
-}
-#endif /* RNG */
-
-#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
-/**
-  * @brief  Return PLL clock frequency used for USB domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_USB(void)
-{
-  uint32_t pllinputfreq;
-  uint32_t pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
-
-     RNG Domain clock = PLL_VCO / PLLQ
-  */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_USB_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
-                                       LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
-}
-#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
-
-#if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL)
-/**
-  * @brief  Return PLL clock frequency used for TIM1 domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_TIM1(void)
-{
-  uint32_t pllinputfreq;
-  uint32_t pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
-
-     TIM1 Domain clock = PLL_VCO / PLLQ
-  */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_TIM1_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
-                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
-}
-#endif /* RCC_PLLQ_SUPPORT */
-
-#if defined(RCC_CCIPR_TIM15SEL)
-/**
-  * @brief  Return PLL clock frequency used for TIM15 domain
-  * @retval PLL clock frequency (in Hz)
-  */
-static uint32_t RCC_PLL_GetFreqDomain_TIM15(void)
-{
-  uint32_t pllinputfreq;
-  uint32_t pllsource;
-
-  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
-
-     TIM15 Domain clock = PLL_VCO / PLLQ
-  */
-  pllsource = LL_RCC_PLL_GetMainSource();
-
-  switch (pllsource)
-  {
-    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pllinputfreq = HSE_VALUE;
-      break;
-
-    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-    default:
-      pllinputfreq = HSI_VALUE;
-      break;
-  }
-  return __LL_RCC_CALC_PLLCLK_TIM15_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
-                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
-}
-#endif /* RCC_CCIPR_TIM15SEL */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* RCC */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c

@@ -1,549 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_spi.c
-  * @author  MCD Application Team
-  * @brief   SPI LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_spi.h"
-#include "stm32g0xx_ll_bus.h"
-#include "stm32g0xx_ll_rcc.h"
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3)
-
-/** @addtogroup SPI_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Constants SPI Private Constants
-  * @{
-  */
-/* SPI registers Masks */
-#define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
-                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
-                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
-                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
-                                            SPI_CR1_BIDIMODE)
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Macros SPI Private Macros
-  * @{
-  */
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
-                                                 || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
-                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
-                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
-
-#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
-                                   || ((__VALUE__) == LL_SPI_MODE_SLAVE))
-
-#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
-                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
-
-#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
-                                       || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
-
-#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
-                                    || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
-                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
-                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-
-#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
-                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
-
-#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
-                                       || ((__VALUE__) == LL_SPI_MSB_FIRST))
-
-#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
-                                             || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
-
-#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the SPI registers to their default reset values.
-  * @param  SPIx SPI Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: SPI registers are de-initialized
-  *          - ERROR: SPI registers are not de-initialized
-  */
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-#if defined(SPI1)
-  if (SPIx == SPI1)
-  {
-    /* Force reset of SPI clock */
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
-
-    /* Release reset of SPI clock */
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
-
-    status = SUCCESS;
-  }
-#endif /* SPI1 */
-#if defined(SPI2)
-  if (SPIx == SPI2)
-  {
-    /* Force reset of SPI clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
-
-    /* Release reset of SPI clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
-
-    status = SUCCESS;
-  }
-#endif /* SPI2 */
-#if defined(SPI3)
-  if (SPIx == SPI3)
-  {
-    /* Force reset of SPI clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
-
-    /* Release reset of SPI clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
-
-    status = SUCCESS;
-  }
-#endif /* SPI3 */
-
-  return status;
-}
-
-/**
-  * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
-  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
-  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
-  * @param  SPIx SPI Instance
-  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
-  */
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the SPI Instance SPIx*/
-  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-  /* Check the SPI parameters from SPI_InitStruct*/
-  assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
-  assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
-  assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
-  assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
-  assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
-  assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
-  assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
-  assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
-  assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
-
-  if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
-  {
-    /*---------------------------- SPIx CR1 Configuration ------------------------
-     * Configure SPIx CR1 with parameters:
-     * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
-     * - Master/Slave Mode:  SPI_CR1_MSTR bit
-     * - ClockPolarity:      SPI_CR1_CPOL bit
-     * - ClockPhase:         SPI_CR1_CPHA bit
-     * - NSS management:     SPI_CR1_SSM bit
-     * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
-     * - BitOrder:           SPI_CR1_LSBFIRST bit
-     * - CRCCalculation:     SPI_CR1_CRCEN bit
-     */
-    MODIFY_REG(SPIx->CR1,
-               SPI_CR1_CLEAR_MASK,
-               SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
-               SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
-               SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
-               SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
-
-    /*---------------------------- SPIx CR2 Configuration ------------------------
-     * Configure SPIx CR2 with parameters:
-     * - DataWidth:          DS[3:0] bits
-     * - NSS management:     SSOE bit
-     */
-    MODIFY_REG(SPIx->CR2,
-               SPI_CR2_DS | SPI_CR2_SSOE,
-               SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
-
-    /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
-    if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
-    {
-      LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
-    }
-
-    /*---------------------------- SPIx CRCPR Configuration ----------------------
-     * Configure SPIx CRCPR with parameters:
-     * - CRCPoly:            CRCPOLY[15:0] bits
-     */
-    if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
-    {
-      assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
-      LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
-    }
-    status = SUCCESS;
-  }
-
-#if defined (SPI_I2S_SUPPORT)
-  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
-  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2S_SUPPORT */
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
-  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
-  * whose fields will be set to default values.
-  * @retval None
-  */
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
-{
-  /* Set SPI_InitStruct fields to default values */
-  SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
-  SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
-  SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
-  SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
-  SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
-  SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
-  SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
-  SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
-  SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
-  SPI_InitStruct->CRCPoly           = 7U;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup I2S_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Constants I2S Private Constants
-  * @{
-  */
-/* I2S registers Masks */
-#define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
-                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
-                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
-
-#define I2S_I2SPR_CLEAR_MASK               0x0002U
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Macros I2S Private Macros
-  * @{
-  */
-
-#define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
-                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
-                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
-                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
-
-#define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
-                                          || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-
-#define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
-                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-
-#define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
-                                          || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
-                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
-                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
-
-#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
-                                          || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
-                                          && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
-                                         || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
-
-#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
-                                               || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2S_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize the SPI/I2S registers to their default reset values.
-  * @param  SPIx SPI Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: SPI registers are de-initialized
-  *          - ERROR: SPI registers are not de-initialized
-  */
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
-{
-  return LL_SPI_DeInit(SPIx);
-}
-
-/**
-  * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
-  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
-  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
-  * @param  SPIx SPI Instance
-  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: SPI registers are Initialized
-  *          - ERROR: SPI registers are not Initialized
-  */
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
-{
-  uint32_t i2sdiv = 2U;
-  uint32_t i2sodd = 0U;
-  uint32_t packetlength = 1U;
-  uint32_t tmp;
-  LL_RCC_ClocksTypeDef rcc_clocks;
-  uint32_t sourceclock;
-  ErrorStatus status = ERROR;
-
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
-  assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
-  assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
-  assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
-  assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
-  assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
-  assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
-
-  if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
-  {
-    /*---------------------------- SPIx I2SCFGR Configuration --------------------
-     * Configure SPIx I2SCFGR with parameters:
-     * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
-     * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
-     * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
-     * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
-     */
-
-    /* Write to SPIx I2SCFGR */
-    MODIFY_REG(SPIx->I2SCFGR,
-               I2S_I2SCFGR_CLEAR_MASK,
-               I2S_InitStruct->Mode | I2S_InitStruct->Standard |
-               I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
-               SPI_I2SCFGR_I2SMOD);
-
-    /*---------------------------- SPIx I2SPR Configuration ----------------------
-     * Configure SPIx I2SPR with parameters:
-     * - MCLKOutput:    SPI_I2SPR_MCKOE bit
-     * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
-     */
-
-    /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
-     * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
-     */
-    if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
-    {
-      /* Check the frame length (For the Prescaler computing)
-       * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
-       */
-      if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
-      {
-        /* Packet length is 32 bits */
-        packetlength = 2U;
-      }
-
-      /* I2S Clock source is System clock: Get System Clock frequency */
-      LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-
-      /* Get the source clock value: based on System Clock value */
-      sourceclock = rcc_clocks.SYSCLK_Frequency;
-
-      /* Compute the Real divider depending on the MCLK output state with a floating point */
-      if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
-      {
-        /* MCLK output is enabled */
-        tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
-      }
-      else
-      {
-        /* MCLK output is disabled */
-        tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
-      }
-
-      /* Remove the floating point */
-      tmp = tmp / 10U;
-
-      /* Check the parity of the divider */
-      i2sodd = (tmp & (uint16_t)0x0001U);
-
-      /* Compute the i2sdiv prescaler */
-      i2sdiv = ((tmp - i2sodd) / 2U);
-
-      /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-      i2sodd = (i2sodd << 8U);
-    }
-
-    /* Test if the divider is 1 or 0 or greater than 0xFF */
-    if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
-    {
-      /* Set the default values */
-      i2sdiv = 2U;
-      i2sodd = 0U;
-    }
-
-    /* Write to SPIx I2SPR register the computed value */
-    WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
-
-    status = SUCCESS;
-  }
-  return status;
-}
-
-/**
-  * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
-  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
-  *         whose fields will be set to default values.
-  * @retval None
-  */
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
-{
-  /*--------------- Reset I2S init structure parameters values -----------------*/
-  I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
-  I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
-  I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
-  I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
-  I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
-  I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
-}
-
-/**
-  * @brief  Set linear and parity prescaler.
-  * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
-  *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
-  * @param  SPIx SPI Instance
-  * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
-  * @param  PrescalerParity This parameter can be one of the following values:
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
-  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
-  * @retval None
-  */
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
-{
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
-  assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
-  assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
-
-  /* Write to SPIx I2SPR */
-  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c

@@ -1,1371 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_tim.c
-  * @author  MCD Application Team
-  * @brief   TIM LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_tim.h"
-#include "stm32g0xx_ll_bus.h"
-
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) ||  defined (TIM14) ||  defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
-
-/** @addtogroup TIM_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup TIM_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
-                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
-
-#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
-                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
-                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
-
-#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
-
-#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
-                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
-
-#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
-                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
-
-#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
-                                          || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
-
-#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
-                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
-                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
-
-#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
-                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
-                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
-                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
-
-#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
-                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
-
-#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
-                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
-                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
-
-#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
-                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
-                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
-
-#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
-                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
-
-#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
-                                         || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
-
-#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
-                                         || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
-
-#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
-                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
-                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
-                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
-
-#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
-                                          || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
-
-#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
-                                             || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
-
-#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
-                                           || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
-
-#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT)          \
-                                           || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
-
-#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
-                                           || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
-
-#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
-                                              || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
-
-#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
-
-#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT)       \
-                                            || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
-
-#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
-                                                     || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
-/**
-  * @}
-  */
-
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup TIM_LL_Private_Functions TIM Private Functions
-  * @{
-  */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIM_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  Set TIMx registers to their reset values.
-  * @param  TIMx Timer instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: invalid TIMx instance
-  */
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
-{
-  ErrorStatus result = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(TIMx));
-
-  if (TIMx == TIM1)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
-  }
-#if defined(TIM2)
-  else if (TIMx == TIM2)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
-  }
-#endif /* TIM2 */
-#if defined(TIM3)
-  else if (TIMx == TIM3)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
-  }
-#endif /* TIM3 */
-#if defined(TIM4)
-  else if (TIMx == TIM4)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
-  }
-#endif /* TIM4 */
-#if defined(TIM6)
-  else if (TIMx == TIM6)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
-  }
-#endif /* TIM6 */
-#if defined(TIM7)
-  else if (TIMx == TIM7)
-  {
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
-  }
-#endif /* TIM7 */
-  else if (TIMx == TIM14)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM14);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM14);
-  }
-#if defined(TIM15)
-  else if (TIMx == TIM15)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
-  }
-#endif /* TIM15 */
-  else if (TIMx == TIM16)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
-  }
-#if defined(TIM17)
-  else if (TIMx == TIM17)
-  {
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
-  }
-#endif /* TIM17 */
-  else
-  {
-    result = ERROR;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Set the fields of the time base unit configuration data structure
-  *         to their default values.
-  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
-  * @retval None
-  */
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
-{
-  /* Set the default configuration */
-  TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
-  TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
-  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
-  TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
-  TIM_InitStruct->RepetitionCounter = 0x00000000U;
-}
-
-/**
-  * @brief  Configure the TIMx time base unit.
-  * @param  TIMx Timer Instance
-  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
-  *         (TIMx time base unit configuration data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
-{
-  uint32_t tmpcr1;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
-  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
-
-  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
-
-  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
-  {
-    /* Select the Counter Mode */
-    MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
-  }
-
-  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
-  {
-    /* Set the clock division */
-    MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
-  }
-
-  /* Write to TIMx CR1 */
-  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
-
-  /* Set the Autoreload value */
-  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
-
-  /* Set the Prescaler value */
-  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
-
-  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
-  {
-    /* Set the Repetition Counter value */
-    LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
-  }
-
-  /* Generate an update event to reload the Prescaler
-     and the repetition counter value (if applicable) immediately */
-  LL_TIM_GenerateEvent_UPDATE(TIMx);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set the fields of the TIMx output channel configuration data
-  *         structure to their default values.
-  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
-  *         (the output channel configuration data structure)
-  * @retval None
-  */
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
-  /* Set the default configuration */
-  TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
-  TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
-  TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
-  TIM_OC_InitStruct->CompareValue = 0x00000000U;
-  TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
-  TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
-  TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
-  TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
-}
-
-/**
-  * @brief  Configure the TIMx output channel.
-  * @param  TIMx Timer Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  *         @arg @ref LL_TIM_CHANNEL_CH5
-  *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
-  *         data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx output channel is initialized
-  *          - ERROR: TIMx output channel is not initialized
-  */
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
-  ErrorStatus result = ERROR;
-
-  switch (Channel)
-  {
-    case LL_TIM_CHANNEL_CH1:
-      result = OC1Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH2:
-      result = OC2Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH3:
-      result = OC3Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH4:
-      result = OC4Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH5:
-      result = OC5Config(TIMx, TIM_OC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH6:
-      result = OC6Config(TIMx, TIM_OC_InitStruct);
-      break;
-    default:
-      break;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Set the fields of the TIMx input channel configuration data
-  *         structure to their default values.
-  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
-  *         data structure)
-  * @retval None
-  */
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Set the default configuration */
-  TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
-  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
-  TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
-  TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
-  * @brief  Configure the TIMx input channel.
-  * @param  TIMx Timer Instance
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_TIM_CHANNEL_CH1
-  *         @arg @ref LL_TIM_CHANNEL_CH2
-  *         @arg @ref LL_TIM_CHANNEL_CH3
-  *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
-  *         structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx output channel is initialized
-  *          - ERROR: TIMx output channel is not initialized
-  */
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
-{
-  ErrorStatus result = ERROR;
-
-  switch (Channel)
-  {
-    case LL_TIM_CHANNEL_CH1:
-      result = IC1Config(TIMx, TIM_IC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH2:
-      result = IC2Config(TIMx, TIM_IC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH3:
-      result = IC3Config(TIMx, TIM_IC_InitStruct);
-      break;
-    case LL_TIM_CHANNEL_CH4:
-      result = IC4Config(TIMx, TIM_IC_InitStruct);
-      break;
-    default:
-      break;
-  }
-
-  return result;
-}
-
-/**
-  * @brief  Fills each TIM_EncoderInitStruct field with its default value
-  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
-  *         configuration data structure)
-  * @retval None
-  */
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
-  /* Set the default configuration */
-  TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
-  TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
-  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
-  TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
-  TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
-  TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
-  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
-  TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
-  TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
-  * @brief  Configure the encoder interface of the timer instance.
-  * @param  TIMx Timer Instance
-  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
-  *         configuration data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
-  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
-  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
-
-  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
-  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Configure TI1 */
-  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
-
-  /* Configure TI2 */
-  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
-  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
-
-  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
-  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
-  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
-  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
-  /* Set encoder mode */
-  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set the fields of the TIMx Hall sensor interface configuration data
-  *         structure to their default values.
-  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
-  *         configuration data structure)
-  * @retval None
-  */
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
-  /* Set the default configuration */
-  TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
-  TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
-  TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
-  TIM_HallSensorInitStruct->CommutationDelay  = 0U;
-}
-
-/**
-  * @brief  Configure the Hall sensor interface of the timer instance.
-  * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
-  *       to the TI1 input channel
-  * @note TIMx slave mode controller is configured in reset mode.
-          Selected internal trigger is TI1F_ED.
-  * @note Channel 1 is configured as input, IC1 is mapped on TRC.
-  * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
-  *       between 2 changes on the inputs. It gives information about motor speed.
-  * @note Channel 2 is configured in output PWM 2 mode.
-  * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
-  * @note OC2REF is selected as trigger output on TRGO.
-  * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
-  *       when TIMx operates in Hall sensor interface mode.
-  * @param  TIMx Timer Instance
-  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
-  *         interface configuration data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
-  uint32_t tmpcr2;
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-  uint32_t tmpsmcr;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
-  assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
-
-  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
-  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
-
-  /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
-  tmpcr2 |= TIM_CR2_TI1S;
-
-  /* OC2REF signal is used as trigger output (TRGO) */
-  tmpcr2 |= LL_TIM_TRGO_OC2REF;
-
-  /* Configure the slave mode controller */
-  tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
-  tmpsmcr |= LL_TIM_TS_TI1F_ED;
-  tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
-
-  /* Configure input channel 1 */
-  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
-  tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
-  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
-  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
-
-  /* Configure input channel 2 */
-  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
-  tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
-
-  /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
-  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
-  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx SMCR */
-  LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  /* Write to TIMx CCR2 */
-  LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Set the fields of the Break and Dead Time configuration data structure
-  *         to their default values.
-  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
-  *         data structure)
-  * @retval None
-  */
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
-  /* Set the default configuration */
-  TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
-  TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
-  TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
-  TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
-  TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
-  TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
-  TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
-  TIM_BDTRInitStruct->BreakAFMode     = LL_TIM_BREAK_AFMODE_INPUT;
-  TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
-  TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
-  TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
-  TIM_BDTRInitStruct->Break2AFMode    = LL_TIM_BREAK2_AFMODE_INPUT;
-  TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
-}
-
-/**
-  * @brief  Configure the Break and Dead Time feature of the timer instance.
-  * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
-  *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
-  *  can be necessary to configure all of them during the first write access to
-  *  the TIMx_BDTR register.
-  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a break input.
-  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
-  *       a timer instance provides a second break input.
-  * @param  TIMx Timer Instance
-  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
-  *         data structure)
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Break and Dead Time is initialized
-  *          - ERROR: not applicable
-  */
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
-  uint32_t tmpbdtr = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
-  assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
-  assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
-  assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
-  assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
-  assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
-
-  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
-  the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
-  /* Set the BDTR bits */
-  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
-  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
-  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
-  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
-  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
-  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
-  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
-  MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
-  if (IS_TIM_ADVANCED_INSTANCE(TIMx))
-  {
-    assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
-    assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
-  }
-
-  if (IS_TIM_BKIN2_INSTANCE(TIMx))
-  {
-    assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
-    assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
-    assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
-    assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
-
-    /* Set the BREAK2 input related BDTR bit-fields */
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
-  }
-
-  /* Set TIMx_BDTR */
-  LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
-
-  return SUCCESS;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
-  *  @brief   Private functions
-  * @{
-  */
-/**
-  * @brief  Configure the TIMx output channel 1.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
-
-  /* Set the Output Compare Mode */
-  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
-
-  if (IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
-    /* Set the complementary output Polarity */
-    MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
-
-    /* Set the complementary output State */
-    MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
-
-    /* Set the Output Idle state */
-    MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
-
-    /* Set the complementary output Idle state */
-    MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
-  }
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 2.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
-
-  if (IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
-    /* Set the complementary output Polarity */
-    MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
-
-    /* Set the complementary output State */
-    MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
-
-    /* Set the Output Idle state */
-    MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
-
-    /* Set the complementary output Idle state */
-    MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
-  }
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR1 */
-  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 3.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
-
-  if (IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
-    /* Set the complementary output Polarity */
-    MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
-
-    /* Set the complementary output State */
-    MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
-
-    /* Set the Output Idle state */
-    MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
-
-    /* Set the complementary output Idle state */
-    MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
-  }
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR2 */
-  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 4.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr2;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
-  /* Reset Capture/Compare selection Bits */
-  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
-
-  if (IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
-    /* Set the Output Idle state */
-    MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
-  }
-
-  /* Write to TIMx CR2 */
-  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
-  /* Write to TIMx CCMR2 */
-  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 5.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr3;
-  uint32_t tmpccer;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC5_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-
-  /* Disable the Channel 5: Reset the CC5E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CCMR3 register value */
-  tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
-
-  if (IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
-    /* Set the Output Idle state */
-    MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
-
-  }
-
-  /* Write to TIMx CCMR3 */
-  LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx output channel 6.
-  * @param  TIMx Timer Instance
-  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
-  uint32_t tmpccmr3;
-  uint32_t tmpccer;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC6_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-
-  /* Disable the Channel 5: Reset the CC6E Bit */
-  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
-
-  /* Get the TIMx CCER register value */
-  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
-  /* Get the TIMx CCMR3 register value */
-  tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
-
-  /* Select the Output Compare Mode */
-  MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
-
-  /* Set the Output Compare Polarity */
-  MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
-
-  /* Set the Output State */
-  MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
-
-  if (IS_TIM_BREAK_INSTANCE(TIMx))
-  {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
-    /* Set the Output Idle state */
-    MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
-  }
-
-  /* Write to TIMx CCMR3 */
-  LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
-
-  /* Set the Capture Compare Register value */
-  LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
-
-  /* Write to TIMx CCER */
-  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 1.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR1,
-             (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
-  /* Select the Polarity and set the CC1E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC1P | TIM_CCER_CC1NP),
-             (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 2.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR1,
-             (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
-  /* Select the Polarity and set the CC2E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC2P | TIM_CCER_CC2NP),
-             ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 3.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR2,
-             (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
-  /* Select the Polarity and set the CC3E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC3P | TIM_CCER_CC3NP),
-             ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
-
-  return SUCCESS;
-}
-
-/**
-  * @brief  Configure the TIMx input channel 4.
-  * @param  TIMx Timer Instance
-  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: TIMx registers are de-initialized
-  *          - ERROR: not applicable
-  */
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
-  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
-  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
-  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
-  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
-
-  /* Select the Input and set the filter and the prescaler value */
-  MODIFY_REG(TIMx->CCMR2,
-             (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
-             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
-  /* Select the Polarity and set the CC2E Bit */
-  MODIFY_REG(TIMx->CCER,
-             (TIM_CCER_CC4P | TIM_CCER_CC4NP),
-             ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
-
-  return SUCCESS;
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c

@@ -1,470 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_usart.c
-  * @author  MCD Application Team
-  * @brief   USART LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_usart.h"
-#include "stm32g0xx_ll_rcc.h"
-#include "stm32g0xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6)
-
-/** @addtogroup USART_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Macros
-  * @{
-  */
-
-#define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
-                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
-
-/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
- *              divided by the smallest oversampling used on the USART (i.e. 8)    */
-#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
-
-/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
-#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
-
-#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
-                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
-                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
-                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
-
-#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
-                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
-                                       || ((__VALUE__) == LL_USART_PARITY_ODD))
-
-#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
-                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
-                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
-
-#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
-                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
-
-#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
-                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
-
-#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
-                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))
-
-#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
-                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))
-
-#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
-                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
-
-#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
-                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
-                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
-                                         || ((__VALUE__) == LL_USART_STOPBITS_2))
-
-#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
-                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
-                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
-                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup USART_LL_EF_Init
-  * @{
-  */
-
-/**
-  * @brief  De-initialize USART registers (Registers restored to their default values).
-  * @param  USARTx USART Instance
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: USART registers are de-initialized
-  *          - ERROR: USART registers are not de-initialized
-  */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(USARTx));
-
-  if (USARTx == USART1)
-  {
-    /* Force reset of USART clock */
-    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
-
-    /* Release reset of USART clock */
-    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
-  }
-  else if (USARTx == USART2)
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
-  }
-#if defined(USART3)
-  else if (USARTx == USART3)
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
-  }
-#endif /* USART3 */
-#if defined(USART4)
-  else if (USARTx == USART4)
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
-  }
-#endif /* USART4 */
-#if defined(USART5)
-  else if (USARTx == USART5)
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
-  }
-#endif /* USART5 */
-#if defined(USART6)
-  else if (USARTx == USART6)
-  {
-    /* Force reset of USART clock */
-    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART6);
-
-    /* Release reset of USART clock */
-    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART6);
-  }
-#endif /* USART6 */
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief  Initialize USART registers according to the specified
-  *         parameters in USART_InitStruct.
-  * @note   As some bits in USART configuration registers can only be written when
-  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
-  *         this function. Otherwise, ERROR result will be returned.
-  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
-  * @param  USARTx USART Instance
-  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
-  *         that contains the configuration information for the specified USART peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
-  *          - ERROR: Problem occurred during USART Registers initialization
-  */
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
-{
-  ErrorStatus status = ERROR;
-  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
-#if !defined(RCC_CCIPR_USART3SEL)&&!defined(RCC_CCIPR_USART4SEL)||(!defined(RCC_CCIPR_USART2SEL))||!defined(RCC_CCIPR_USART5SEL)||!defined(RCC_CCIPR_USART6SEL)
-  LL_RCC_ClocksTypeDef RCC_Clocks;
-#endif
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(USARTx));
-  assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
-  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
-  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
-  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
-  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
-  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
-  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
-  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
-
-  /* USART needs to be in disabled state, in order to be able to configure some bits in
-     CRx registers */
-  if (LL_USART_IsEnabled(USARTx) == 0U)
-  {
-    /*---------------------------- USART CR1 Configuration ---------------------
-     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
-     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
-     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
-     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
-     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
-     */
-    MODIFY_REG(USARTx->CR1,
-               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
-                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
-               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
-                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
-
-    /*---------------------------- USART CR2 Configuration ---------------------
-     * Configure USARTx CR2 (Stop bits) with parameters:
-     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
-     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
-     */
-    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
-
-    /*---------------------------- USART CR3 Configuration ---------------------
-     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
-     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
-     *   USART_InitStruct->HardwareFlowControl value.
-     */
-    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
-
-    /*---------------------------- USART BRR Configuration ---------------------
-     * Retrieve Clock frequency used for USART Peripheral
-     */
-    if (USARTx == USART1)
-    {
-      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
-    }
-    else if (USARTx == USART2)
-    {
-#if defined(RCC_CCIPR_USART2SEL)
-      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
-#else
-      /* USART2 clock is PCLK */
-      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
-      periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
-    }
-#if defined(USART3)
-    else if (USARTx == USART3)
-    {
-#if defined(RCC_CCIPR_USART3SEL)
-      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
-#else
-      /* USART3 clock is PCLK */
-      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
-      periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
-    }
-#endif /* USART3 */
-#if defined(USART4)
-    else if (USARTx == USART4)
-    {
-#if defined(RCC_CCIPR_USART4SEL)
-      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART4_CLKSOURCE);
-#else
-      /* USART4 clock is PCLK1 */
-      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
-      periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif /* RCC_CCIPR_USART4SEL */
-    }
-#endif /* USART4 */
-#if defined(USART5)
-    else if (USARTx == USART5)
-    {
-      /* USART5 clock is PCLK1 */
-      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
-      periphclk = RCC_Clocks.PCLK1_Frequency;
-    }
-#endif /* USART5 */
-#if defined(USART6)
-    else if (USARTx == USART6)
-    {
-      /* USART6 clock is PCLK1 */
-      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
-      periphclk = RCC_Clocks.PCLK1_Frequency;
-    }
-#endif /* USART6 */
-    else
-    {
-      /* Nothing to do, as error code is already assigned to ERROR value */
-    }
-
-    /* Configure the USART Baud Rate :
-       - prescaler value is required
-       - valid baud rate value (different from 0) is required
-       - Peripheral clock as returned by RCC service, should be valid (different from 0).
-    */
-    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
-        && (USART_InitStruct->BaudRate != 0U))
-    {
-      status = SUCCESS;
-      LL_USART_SetBaudRate(USARTx,
-                           periphclk,
-                           USART_InitStruct->PrescalerValue,
-                           USART_InitStruct->OverSampling,
-                           USART_InitStruct->BaudRate);
-
-      /* Check BRR is greater than or equal to 16d */
-      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
-    }
-
-    /*---------------------------- USART PRESC Configuration -----------------------
-     * Configure USARTx PRESC (Prescaler) with parameters:
-     * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
-     */
-    LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
-  }
-  /* Endif (=> USART not in Disabled state => return ERROR) */
-
-  return (status);
-}
-
-/**
-  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
-  * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
-  *                         whose fields will be set to default values.
-  * @retval None
-  */
-
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
-{
-  /* Set USART_InitStruct fields to default values */
-  USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
-  USART_InitStruct->BaudRate            = 9600U;
-  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
-  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
-  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
-  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
-  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
-  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
-}
-
-/**
-  * @brief  Initialize USART Clock related settings according to the
-  *         specified parameters in the USART_ClockInitStruct.
-  * @note   As some bits in USART configuration registers can only be written when
-  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
-  *         this function. Otherwise, ERROR result will be returned.
-  * @param  USARTx USART Instance
-  * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
-  *         that contains the Clock configuration information for the specified USART peripheral.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: USART registers related to Clock settings are initialized according
-  *                     to USART_ClockInitStruct content
-  *          - ERROR: Problem occurred during USART Registers initialization
-  */
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check USART Instance and Clock signal output parameters */
-  assert_param(IS_UART_INSTANCE(USARTx));
-  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
-
-  /* USART needs to be in disabled state, in order to be able to configure some bits in
-     CRx registers */
-  if (LL_USART_IsEnabled(USARTx) == 0U)
-  {
-    /* Ensure USART instance is USART capable */
-    assert_param(IS_USART_INSTANCE(USARTx));
-
-    /* Check clock related parameters */
-    assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
-    assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
-    assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
-
-    /*---------------------------- USART CR2 Configuration -----------------------
-     * Configure USARTx CR2 (Clock signal related bits) with parameters:
-     * - Clock Output:                USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
-     * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
-     * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
-     * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
-     */
-    MODIFY_REG(USARTx->CR2,
-               USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
-               USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
-               USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
-  }
-  /* Else (USART not in Disabled state => return ERROR */
-  else
-  {
-    status = ERROR;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
-  * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
-  *                              whose fields will be set to default values.
-  * @retval None
-  */
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
-{
-  /* Set LL_USART_ClockInitStruct fields with default values */
-  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
-  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput =
-                                                                                  LL_USART_CLOCK_DISABLE */
-  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput =
-                                                                                  LL_USART_CLOCK_DISABLE */
-  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput =
-                                                                                  LL_USART_CLOCK_DISABLE */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* USART1 || USART2 || USART3 || USART4 || USART5 || USART6 */
-
-/**
-  * @}
-  */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c

@@ -1,577 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32g0xx_ll_utils.c
-  * @author  MCD Application Team
-  * @brief   UTILS LL module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32g0xx_ll_utils.h"
-#include "stm32g0xx_ll_rcc.h"
-#include "stm32g0xx_ll_system.h"
-#include "stm32g0xx_ll_pwr.h"
-#ifdef  USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-/** @addtogroup STM32G0xx_LL_Driver
-  * @{
-  */
-
-/** @addtogroup UTILS_LL
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Constants
-  * @{
-  */
-#define UTILS_MAX_FREQUENCY          64000000U     /*!< Maximum frequency for system clock, in Hz */
-
-/* Defines used for PLL range */
-#define UTILS_PLLVCO_INPUT_MIN       4000000U      /*!< Frequency min for PLLVCO input, in Hz   */
-#define UTILS_PLLVCO_INPUT_MAX       8000000U      /*!< Frequency max for PLLVCO input, in Hz   */
-#define UTILS_PLLVCO_OUTPUT_MIN      64000000U     /*!< Frequency min for PLLVCO output, in Hz  */
-#define UTILS_PLLVCO_OUTPUT_MAX      344000000U    /*!< Frequency max for PLLVCO output, in Hz  */
-
-/* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN      4000000U      /*!< Frequency min for HSE frequency, in Hz   */
-#define UTILS_HSE_FREQUENCY_MAX      48000000U     /*!< Frequency max for HSE frequency, in Hz   */
-
-/* Defines used for FLASH latency according to HCLK Frequency */
-#define UTILS_SCALE1_LATENCY1_FREQ  24000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
-#define UTILS_SCALE1_LATENCY2_FREQ  48000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
-#define UTILS_SCALE1_LATENCY3_FREQ  64000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Macros
-  * @{
-  */
-#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
-                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
-
-#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
-                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))
-
-#define IS_LL_UTILS_HSI_DIV(__VALUE__)  (((__VALUE__) == LL_RCC_HSI_DIV_1)  \
-                                      || ((__VALUE__) == LL_RCC_HSI_DIV_2)  \
-                                      || ((__VALUE__) == LL_RCC_HSI_DIV_4)  \
-                                      || ((__VALUE__) == LL_RCC_HSI_DIV_8)  \
-                                      || ((__VALUE__) == LL_RCC_HSI_DIV_16) \
-                                      || ((__VALUE__) == LL_RCC_HSI_DIV_32) \
-                                      || ((__VALUE__) == LL_RCC_HSI_DIV_64) \
-                                      || ((__VALUE__) == LL_RCC_HSI_DIV_128))
-
-#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
-                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
-                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
-                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
-                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
-                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
-                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
-                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
-
-#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
-
-#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
-                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \
-                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
-                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_5) \
-                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
-                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_7) \
-                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
-
-#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
-
-#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
-
-#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY)
-
-#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
-                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
-
-#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
-/**
-  * @}
-  */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
-  * @{
-  */
-static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
-                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-static ErrorStatus UTILS_PLL_IsBusy(void);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup UTILS_LL_EF_DELAY
-  * @{
-  */
-
-/**
-  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
-  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
-  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
-  * @param  HCLKFrequency HCLK frequency in Hz
-  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
-  * @retval None
-  */
-void LL_Init1msTick(uint32_t HCLKFrequency)
-{
-  /* Use frequency provided in argument */
-  LL_InitTick(HCLKFrequency, 1000U);
-}
-
-/**
-  * @brief  This function provides accurate delay (in milliseconds) based
-  *         on SysTick counter flag
-  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
-  *         and use rather osDelay service.
-  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
-  *         will configure Systick to 1ms
-  * @param  Delay specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-void LL_mDelay(uint32_t Delay)
-{
-  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
-   uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
-  /* Add this code to indicate that local variable is not used */
-  ((void)tmp);
-  tmpDelay  = Delay;
-  /* Add a period to guaranty minimum wait */
-  if (tmpDelay  < LL_MAX_DELAY)
-  {
-    tmpDelay ++;
-  }
-
-  while (tmpDelay  != 0U)
-  {
-    if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
-    {
-      tmpDelay --;
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup UTILS_EF_SYSTEM
-  *  @brief    System Configuration functions
-  *
-  @verbatim
- ===============================================================================
-           ##### System Configuration functions #####
- ===============================================================================
-    [..]
-         System, AHB and APB buses clocks configuration
-
-         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 is 64000000 Hz.
-  @endverbatim
-  @internal
-             Depending on the device voltage range, the maximum frequency should be
-             adapted accordingly:
-
-             (++)  Table 1. HCLK clock frequency.
-             (++)  +-------------------------------------------------------+
-             (++)  | Latency         |    HCLK clock frequency (MHz)       |
-             (++)  |                 |-------------------------------------|
-             (++)  |                 | voltage range 1  | voltage range 2  |
-             (++)  |                 |   1.08V - 1.32V  |  0.9 V - 1.10V   |
-             (++)  |-----------------|------------------|------------------|
-             (++)  |0WS(1 CPU cycles)|      HCLK <= 24  |      HCLK <= 8   |
-             (++)  |-----------------|------------------|------------------|
-             (++)  |1WS(2 CPU cycles)|      HCLK <= 48  |      HCLK <= 16  |
-             (++)  |-----------------|------------------|------------------|
-             (++)  |2WS(3 CPU cycles)|      HCLK <= 64  |        -         |
-             (++)  |-----------------|------------------|------------------|
-
-  @endinternal
-  * @{
-  */
-
-/**
-  * @brief  This function sets directly SystemCoreClock CMSIS variable.
-  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
-  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
-  * @retval None
-  */
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
-{
-  /* HCLK clock frequency */
-  SystemCoreClock = HCLKFrequency;
-}
-
-/**
-  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
-  * @note   The application need to ensure that PLL is disabled.
-  * @note   Function is based on the following formula:
-  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
-  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
-  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
-  *         - PLLR: ensure that max frequency at 64000000 Hz is reach (PLLVCO_output / PLLR)
-  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
-  *                             the configuration information for the PLL.
-  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
-  *                             the configuration information for the BUS prescalers.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Max frequency configuration done
-  *          - ERROR: Max frequency configuration not done
-  */
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
-                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
-  ErrorStatus status;
-  uint32_t pllfreq;
-
-  /* Check if one of the PLL is enabled */
-  if (UTILS_PLL_IsBusy() == SUCCESS)
-  {
-    /* Calculate the new PLL output frequency */
-    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
-
-    /* Enable HSI if not enabled */
-    if (LL_RCC_HSI_IsReady() != 1U)
-    {
-      LL_RCC_HSI_Enable();
-      while (LL_RCC_HSI_IsReady() != 1U)
-      {
-        /* Wait for HSI ready */
-      }
-    }
-
-    /* Configure PLL */
-    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
-                                UTILS_PLLInitStruct->PLLR);
-
-    /* Enable PLL and switch system clock to PLL */
-    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
-  }
-  else
-  {
-    /* Current PLL configuration cannot be modified */
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  This function configures system clock with HSE as clock source of the PLL
-  * @note   The application need to ensure that PLL is disabled.
-  * @note   Function is based on the following formula:
-  *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
-  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
-  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
-  *         - PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
-  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
-  * @param  HSEBypass This parameter can be one of the following values:
-  *         @arg @ref LL_UTILS_HSEBYPASS_ON
-  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
-  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
-  *                             the configuration information for the PLL.
-  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
-  *                             the configuration information for the BUS prescalers.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Max frequency configuration done
-  *          - ERROR: Max frequency configuration not done
-  */
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
-                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
-  ErrorStatus status;
-  uint32_t pllfreq;
-
-  /* Check the parameters */
-  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
-  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
-
-  /* Check if one of the PLL is enabled */
-  if (UTILS_PLL_IsBusy() == SUCCESS)
-  {
-    /* Calculate the new PLL output frequency */
-    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
-
-    /* Enable HSE if not enabled */
-    if (LL_RCC_HSE_IsReady() != 1U)
-    {
-      /* Check if need to enable HSE bypass feature or not */
-      if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
-      {
-        LL_RCC_HSE_EnableBypass();
-      }
-      else
-      {
-        LL_RCC_HSE_DisableBypass();
-      }
-
-      /* Enable HSE */
-      LL_RCC_HSE_Enable();
-      while (LL_RCC_HSE_IsReady() != 1U)
-      {
-        /* Wait for HSE ready */
-      }
-    }
-
-    /* Configure PLL */
-    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
-                                UTILS_PLLInitStruct->PLLR);
-
-    /* Enable PLL and switch system clock to PLL */
-    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
-  }
-  else
-  {
-    /* Current PLL configuration cannot be modified */
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Update number of Flash wait states in line with new frequency and current
-  *         voltage range.
-  * @param  HCLKFrequency  HCLK frequency
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: Latency has been modified
-  *          - ERROR: Latency cannot be modified
-  */
-ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
-{
-  uint32_t timeout;
-  uint32_t getlatency;
-  uint32_t latency;
-  ErrorStatus status;
-
-  /* Frequency cannot be equal to 0 or greater than max clock */
-  if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ))
-  {
-    status = ERROR;
-  }
-  else
-  {
-    if (HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
-    {
-      /* 48 < HCLK <= 64 => 2WS (3 CPU cycles) */
-      latency = LL_FLASH_LATENCY_2;
-    }
-    else
-    {
-      if (HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
-      {
-        /* 24 < HCLK <= 48 => 1WS (2 CPU cycles) */
-        latency = LL_FLASH_LATENCY_1;
-      }
-      else
-      {
-        /* else HCLKFrequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
-        latency = LL_FLASH_LATENCY_0;
-      }
-    }
-
-    LL_FLASH_SetLatency(latency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-       memory by reading the FLASH_ACR register */
-    timeout = 2u;
-    do
-    {
-      /* Wait for Flash latency to be updated */
-      getlatency = LL_FLASH_GetLatency();
-      timeout--;
-    } while ((getlatency != latency) && (timeout > 0u));
-
-    if(getlatency != latency)
-    {
-      status = ERROR;
-    }
-    else
-    {
-      status = SUCCESS;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup UTILS_LL_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Function to check that PLL can be modified
-  * @param  PLL_InputFrequency  PLL input frequency (in Hz)
-  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
-  *                             the configuration information for the PLL.
-  * @retval PLL output frequency (in Hz)
-  */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
-{
-  uint32_t pllfreq;
-
-  /* Check the parameters */
-  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
-  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
-  assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
-
-  /* Check different PLL parameters according to RM                          */
-  /*  - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz.   */
-  pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
-  assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
-
-  /*  - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
-  pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
-  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
-
-  /*  - PLLR: ensure that max frequency at 64000000 Hz is reached                   */
-  pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U));
-  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
-
-  return pllfreq;
-}
-
-/**
-  * @brief  Function to check that PLL can be modified
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: PLL modification can be done
-  *          - ERROR: PLL is busy
-  */
-static ErrorStatus UTILS_PLL_IsBusy(void)
-{
-  ErrorStatus status = SUCCESS;
-
-  /* Check if PLL is busy*/
-  if (LL_RCC_PLL_IsReady() != 0U)
-  {
-    /* PLL configuration cannot be modified */
-    status = ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Function to enable PLL and switch system clock to PLL
-  * @param  SYSCLK_Frequency SYSCLK frequency
-  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
-  *                             the configuration information for the BUS prescalers.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: No problem to switch system to PLL
-  *          - ERROR: Problem to switch system to PLL
-  */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
-  ErrorStatus status = SUCCESS;
-  uint32_t hclk_frequency;
-
-  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
-  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
-
-  /* Calculate HCLK frequency */
-  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
-
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if (SystemCoreClock < hclk_frequency)
-  {
-    /* Set FLASH latency to highest latency */
-    status = LL_SetFlashLatency(hclk_frequency);
-  }
-
-  /* Update system clock configuration */
-  if (status == SUCCESS)
-  {
-    /* Enable PLL */
-    LL_RCC_PLL_Enable();
-    LL_RCC_PLL_EnableDomain_SYS();
-    while (LL_RCC_PLL_IsReady() != 1U)
-    {
-      /* Wait for PLL ready */
-    }
-
-    /* Sysclk activation on the main PLL */
-    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
-    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
-    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
-    {
-      /* Wait for system clock switch to PLL */
-    }
-
-    /* Set APB1 & APB2 prescaler*/
-    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
-  }
-
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if (SystemCoreClock > hclk_frequency)
-  {
-    /* Set FLASH latency to lowest latency */
-    status = LL_SetFlashLatency(hclk_frequency);
-  }
-
-  /* Update SystemCoreClock variable */
-  if (status == SUCCESS)
-  {
-    LL_SetSystemCoreClock(hclk_frequency);
-  }
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Inc/board.h

@@ -124,9 +124,6 @@
 #define BTNS_STATE          (BTNS1_STATE | BTNS2_STATE)
 
 /* Variables */
-#ifndef __ARMCC_VERSION
-uint32_t SystemCoreClock;
-#endif
 
 /* Type Defs */
 typedef enum {

Inc/gpio.h

@@ -71,25 +71,6 @@
 #define GPIO_PIN_14   0x4000
 #define GPIO_PIN_15   0x8000
 
-/* Bits definition for x32 GPIO PINs */
-#define GPIO32_PIN_0    0x00000001
-#define GPIO32_PIN_1    0x00000004
-#define GPIO32_PIN_2    0x00000010
-#define GPIO32_PIN_3    0x00000040
-#define GPIO32_PIN_4    0x00000100
-#define GPIO32_PIN_5    0x00000400
-#define GPIO32_PIN_6    0x00001000
-#define GPIO32_PIN_7    0x00004000
-#define GPIO32_PIN_8    0x00010000
-#define GPIO32_PIN_9    0x00040000
-#define GPIO32_PIN_10   0x00100000
-#define GPIO32_PIN_11   0x00400000
-#define GPIO32_PIN_12   0x01000000
-#define GPIO32_PIN_13   0x04000000
-#define GPIO32_PIN_14   0x10000000
-#define GPIO32_PIN_15   0x40000000
-
-
 /* functions from stm32g0xx_ll_gpio.h */
 static inline void GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) {
   MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));

Makefile

@@ -48,17 +48,17 @@ Src/ds3231.c \
 Src/bme280.c \
 Src/rtos.c \
 Src/event-system.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_exti.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_i2c.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_pwr.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c \
-Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c \
 Src/system_stm32g0xx.c
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c \
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_exti.c \
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c \
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_i2c.c \
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c \
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c \
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c \
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_pwr.c \
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_tim.c \
+#Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c \
 
 # ASM sources
 ASM_SOURCES =  \

Src/board.c

@@ -166,53 +166,53 @@ void showDigits(uint8_t * dig)
  */
 void HSV2LED(const int hue, const uint8_t sat, const uint8_t val) {
   int base;
-  uint8_t colors[3] = {0};
+  uint8_t r=0, g=0, b=0;
 
   if (sat == 0)
   { // Achromatic color (gray).
-    colors[0] = val;
-    colors[1] = val;
-    colors[2] = val;
+    r = val;
+    g = val;
+    b = val;
   } else {
 
     base = ((255 - sat) * val) >> 8;
     switch (hue / 60) {
     case 0:
-      colors[0] = val;
-      colors[1] = (((val - base) * hue) / 60) + base;
-      colors[2] = base;
+      r = val;
+      g = (((val - base) * hue) / 60) + base;
+      b = base;
       break;
     case 1:
-      colors[0] = (((val - base) * (60 - (hue % 60))) / 60) + base;
-      colors[1] = val;
-      colors[2] = base;
+      r = (((val - base) * (60 - (hue % 60))) / 60) + base;
+      g = val;
+      b = base;
       break;
     case 2:
-      colors[0] = base;
-      colors[1] = val;
-      colors[2] = (((val - base) * (hue % 60)) / 60) + base;
+      r = base;
+      g = val;
+      b = (((val - base) * (hue % 60)) / 60) + base;
       break;
     case 3:
-      colors[0] = base;
-      colors[1] = (((val - base) * (60 - (hue % 60))) / 60) + base;
-      colors[2] = val;
+      r = base;
+      g = (((val - base) * (60 - (hue % 60))) / 60) + base;
+      b = val;
       break;
     case 4:
-      colors[0] = (((val - base) * (hue % 60)) / 60) + base;
-      colors[1] = base;
-      colors[2] = val;
+      r = (((val - base) * (hue % 60)) / 60) + base;
+      g = base;
+      b = val;
       break;
     case 5:
-      colors[0] = val;
-      colors[1] = base;
-      colors[2] = (((val - base) * (60 - (hue % 60))) / 60) + base;
+      r = val;
+      g = base;
+      b = (((val - base) * (60 - (hue % 60))) / 60) + base;
       break;
     }
   }
 
-  COLOR_R(colors[0]);
-  COLOR_G(colors[1]);
-  COLOR_B(colors[2]);
+  COLOR_R(r);
+  COLOR_G(g);
+  COLOR_B(b);
 }
 
 /**

Src/main.c

@@ -215,95 +215,25 @@ void in15Minus(void) {
 }
 
 void MinusFadeIn(void) {
-  static uint8_t cnt = 0;
-
-  TUBE_C_ON;
+  static uint8_t on = 0;
+  static uint8_t off = 20;
+  static uint8_t st = 0;
 
-  switch (cnt) {
-  case 0:
-    IN15_Minus;
-    RTOS_DeleteTask(MinusFadeOut);
-    RTOS_SetTask(MinusFadeIn, 2, 0);
-    break;
-  case 1:
-    IN15_OFF;
-    RTOS_SetTask(MinusFadeIn, 18, 0);
-    break;
-  case 2:
-    IN15_Minus;
-    RTOS_SetTask(MinusFadeIn, 4, 0);
-    break;
-  case 3:
-    IN15_OFF;
-    RTOS_SetTask(MinusFadeIn, 16, 0);
-    break;
-  case 4:
-    IN15_Minus;
-    RTOS_SetTask(MinusFadeIn, 6, 0);
-    break;
-  case 5:
-    IN15_OFF;
-    RTOS_SetTask(MinusFadeIn, 14, 0);
-    break;
-  case 6:
-    IN15_Minus;
-    RTOS_SetTask(MinusFadeIn, 8, 0);
-    break;
-  case 7:
-    IN15_OFF;
-    RTOS_SetTask(MinusFadeIn, 12, 0);
-    break;
-  case 8:
-    IN15_Minus;
-    RTOS_SetTask(MinusFadeIn, 10, 0);
-    break;
-  case 9:
-    IN15_OFF;
-    RTOS_SetTask(MinusFadeIn, 10, 0);
-    break;
-  case 10:
-    IN15_Minus;
-    RTOS_SetTask(MinusFadeIn, 12, 0);
-    break;
-  case 11:
-    IN15_OFF;
-    RTOS_SetTask(MinusFadeIn, 8, 0);
-    break;
-  case 12:
-    IN15_Minus;
-    RTOS_SetTask(MinusFadeIn, 14, 0);
-    break;
-  case 13:
-    IN15_OFF;
-    RTOS_SetTask(MinusFadeIn, 6, 0);
-    break;
-  case 14:
-    IN15_Minus;
-    RTOS_SetTask(MinusFadeIn, 16, 0);
-    break;
-  case 15:
-    IN15_OFF;
-    RTOS_SetTask(MinusFadeIn, 4, 0);
-    break;
-  case 16:
+  if (st == 0) {
+    st = 1;
     IN15_Minus;
-    RTOS_SetTask(MinusFadeIn, 18, 0);
-    break;
-  case 17:
+    on += 2;
+    if (on < 20) {
+      RTOS_SetTask(MinusFadeIn, on, 0);
+    } else {
+      on = 0; off = 20; st = 0;
+    }
+  } else {
+    st = 0;
     IN15_OFF;
-    RTOS_SetTask(MinusFadeIn, 2, 0);
-    break;
-  case 18:
-    IN15_Minus;
-    cnt = 0;
-    return;
-    break;
-  
-  default:
-    cnt = 0;
-    break;
+    off -= 2;
+    RTOS_SetTask(MinusFadeIn, off, 0);
   }
-  cnt ++;
 }
 
 void MinusFadeOut(void) {
@@ -356,16 +286,10 @@ void showTime(void) {
   RTOS_SetTask(MinusFadeOut, 500, 0);
 
   uint8_t buf[4];
-/*
   buf[Tube_A] = Clock.Hr >> 4;
   buf[Tube_B] = Clock.Hr & 0xf;
   buf[Tube_D] = Clock.Min >> 4;
   buf[Tube_E] = Clock.Min & 0xf;
-*/
-  buf[Tube_A] = Clock.Min >> 4;
-  buf[Tube_B] = Clock.Min & 0xf;
-  buf[Tube_D] = Clock.Sec >> 4;
-  buf[Tube_E] = Clock.Sec & 0xf;
   showDigits(buf);
 }