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@@ -42,6 +42,9 @@ typedef enum {
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/* Private macro -------------------------------------------------------------*/
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/* USER CODE BEGIN PM */
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#define SPI_BUFFER_SIZE 5
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+
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+#define I2C_RX_BUF_SIZE 18
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+#define I2C_TX_BUF_SIZE 7
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/* USER CODE END PM */
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/* Private variables ---------------------------------------------------------*/
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@@ -70,6 +73,8 @@ static const uint16_t nixieCathodeMap[4][10] = {
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};
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static const uint8_t nixieCathodeMask[4][2] = {{0x00, 0x3f}, {0xc0, 0x0f}, {0xf0, 0x03}, {0xc0, 0x00}};
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static uint8_t tubesBuffer[SPI_BUFFER_SIZE];
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+static uint8_t i2cBufTX[I2C_TX_BUF_SIZE];
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+static uint8_t i2cBufRX[I2C_RX_BUF_SIZE];
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/* USER CODE END PV */
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@@ -86,6 +91,8 @@ static void MX_TIM17_Init(void);
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/* USER CODE BEGIN PFP */
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static void showDigit(tube_pos_t pos, uint8_t dig);
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static void SPI_StartTX(void);
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+static void RTC_Init(void);
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+static void RTC_ReadAll(void);
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/* USER CODE END PFP */
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/* Private user code ---------------------------------------------------------*/
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@@ -140,7 +147,8 @@ int main(void)
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MX_TIM16_Init();
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MX_TIM17_Init();
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/* USER CODE BEGIN 2 */
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- __enable_irq();
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+ RTC_Init();
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+ // __enable_irq();
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//LL_Init1msTick(rcc_clocks.HCLK_Frequency);
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//LL_mDelay(1);
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@@ -158,56 +166,74 @@ int main(void)
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TUBE_PWR_ON;
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/* Set DMA source and destination addresses. */
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- /* Source: Address of the framebuffer. */
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- DMA1_Channel1->CMAR = (uint32_t)&tubesBuffer;
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+ /* Source: Address of the SPI buffer. */
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+ DMA1_Channel1->CMAR = (uint32_t)&tubesBuffer;
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/* Destination: SPI1 data register. */
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- DMA1_Channel1->CPAR = (uint32_t)&( SPI1->DR );
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- /* Set DMA data transfer length (framebuffer length). */
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+ DMA1_Channel1->CPAR = (uint32_t)&(SPI1->DR);
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+ /* Set DMA data transfer length (SPI buffer length). */
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DMA1_Channel1->CNDTR = SPI_BUFFER_SIZE;
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-#ifdef USE_LL_DRV
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- /* Set DMA transfer addresses of source and destination */
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- LL_DMA_ConfigAddresses(DMA1,
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- LL_DMA_CHANNEL_1,
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- (uint32_t)&tubesBuffer,
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- (uint32_t)&(SPI1->DR),
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- LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
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- /* Set DMA transfer size */
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- LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_1, SPI_BUFFER_SIZE);
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-#endif // USE_LL_DRV
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-
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- /* Start SPI transfer */
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+ /* Source: Address of the I2C RX buffer. */
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+ DMA1_Channel2->CMAR = (uint32_t)&i2cBufRX;
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+ /* Destination: I2C RX data register. */
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+ DMA1_Channel2->CPAR = (uint32_t)&(I2C1->RXDR);
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+ /* Set DMA data transfer length (I2C RX buffer length). */
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+ DMA1_Channel2->CNDTR = I2C_RX_BUF_SIZE; //?
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+
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+ /* Source: Address of the I2C TX buffer. */
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+ DMA1_Channel3->CMAR = (uint32_t)&i2cBufTX;
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+ /* Destination: I2C TX data register. */
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+ DMA1_Channel3->CPAR = (uint32_t)&(I2C1->TXDR);
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+ /* Set DMA data transfer length (I2C TX buffer length). */
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+ DMA1_Channel3->CNDTR = I2C_TX_BUF_SIZE; //?
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+
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+ /* Enable SPI+DMA transfer */
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SPI1->CR2 |= SPI_CR2_TXDMAEN;
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SPI1->CR1 |= SPI_CR1_SPE;
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+ /* Enable DMA channels for I2C */
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+ DMA1_Channel2->CCR |= DMA_CCR_EN; // LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
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+ DMA1_Channel3->CCR |= DMA_CCR_EN; // LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_3);
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+ /* */
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IN15_OFF;
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/* USER CODE END 2 */
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- /* Infinite loop */
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/* USER CODE BEGIN WHILE */
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+ /* Infinite loop */
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while (1)
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{
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- IN15_Plus;
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+ IN15_OFF;
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COLOR_RGB(0, 0, 0);
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LL_mDelay(500);
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-
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+/*
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showDigit(Tube_A, 1);
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showDigit(Tube_B, 2);
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showDigit(Tube_D, 3);
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showDigit(Tube_E, 4);
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SPI_StartTX();
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+*/
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+ RTC_ReadAll();
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- IN15_OFF;
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+ if (Flag.RTC_IRQ != 0) {
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+ Flag.RTC_IRQ = 0;
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+ IN15_Minus;
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+ }
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COLOR_RGB(0xFF, 0x12, 0x0); // FF7E00 or FFBF00
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LL_mDelay(500);
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/* USER CODE END WHILE */
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/* USER CODE BEGIN 3 */
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+/*
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showDigit(Tube_A, 5);
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showDigit(Tube_B, 6);
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showDigit(Tube_D, 7);
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showDigit(Tube_E, 8);
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+*/
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+ showDigit(Tube_A, i2cBufRX[1] >> 4);
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+ showDigit(Tube_B, i2cBufRX[1] & 0xf);
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+ showDigit(Tube_D, i2cBufRX[0] >> 4);
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+ showDigit(Tube_E, i2cBufRX[0] & 0xf);
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SPI_StartTX();
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//__WFI();
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@@ -220,6 +246,48 @@ static void SPI_StartTX(void) {
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LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
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}
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+static void RTC_Init(void) {
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+ /* Clear flags */
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+ Flag.I2C_RX_End = 0;
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+ Flag.I2C_TX_End = 0;
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+
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+ /* Wait for I2C */
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+ while ( I2C1->ISR & I2C_ISR_BUSY ) {};
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+
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+ /* Fill buffer with register address and register value */
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+ i2cBufTX[0] = DS3231_CONTROL_ADDR;
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+ i2cBufTX[1] = DS3231_CONV;
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+
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+ /* Set AUTOEND mode, the device address and number bytes to send. */
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+// I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES | AUTOEND );
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+ I2C1->CR2 = ( I2C_CR2_AUTOEND | I2C_ADDR_RTC << I2C_CR2_SADD_Pos | 2 << I2C_CR2_NBYTES_Pos );
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+ /* Enable I2C DMA requests. */
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+ I2C1->CR1 |= ( I2C_CR1_TXDMAEN );
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+ /* Send a start signal. */
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+ I2C1->CR2 |= ( I2C_CR2_START );
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+ /* (DMA is now running.) */
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+}
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+
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+static void RTC_ReadAll(void) {
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+ while ( I2C1->ISR & I2C_ISR_BUSY ) {};
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+
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+ LL_I2C_SetSlaveAddr(I2C1, I2C_ADDR_RTC);
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+ LL_I2C_SetTransferRequest(I2C1, LL_I2C_REQUEST_WRITE);
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+ LL_I2C_SetTransferSize(I2C1, 1);
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+ i2cBufTX[0] = DS3231_CALENDAR_ADDR;
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+ LL_I2C_EnableDMAReq_TX(I2C1);
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+ LL_I2C_GenerateStartCondition(I2C1);
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+
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+ while ( I2C1->ISR & I2C_ISR_BUSY ) {};
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+
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+ Flag.I2C_RX_End = 0;
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+ Flag.I2C_TX_End = 0;
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+
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+ LL_I2C_SetTransferRequest(I2C1, LL_I2C_REQUEST_READ);
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+ LL_I2C_SetTransferSize(I2C1, 7); // Clock + Calendar = 7 bytes
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+ LL_I2C_EnableDMAReq_RX(I2C1);
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+ LL_I2C_GenerateStartCondition(I2C1);
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+}
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/**
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* @brief System Clock Configuration
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@@ -337,6 +405,11 @@ static void MX_I2C1_Init(void)
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LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MDATAALIGN_BYTE);
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/* USER CODE BEGIN I2C1_Init 1 */
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+ /* Enable DMA transfer complete/error interrupts */
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+ LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_2);
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+ LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_2);
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+ LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_3);
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+ LL_DMA_EnableIT_TE(DMA1, LL_DMA_CHANNEL_3);
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/* USER CODE END I2C1_Init 1 */
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/** I2C Initialization
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