Added DS18B20 support.

Makefile

@@ -90,6 +90,7 @@ MCU  = cortex-m3
 
 # Imported source files and paths.
 CHIBIOS  := C:/MCU/ChibiOS_21.11.3
+CHIBIOS_CONTRIB = $(CHIBIOS)/community
 CONFDIR  := ./cfg
 BUILDDIR := ./build
 DEPDIR   := ./.dep
@@ -99,8 +100,10 @@ include $(CHIBIOS)/os/license/license.mk
 # Startup files.
 include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk
 # HAL-OSAL files (optional).
-include $(CHIBIOS)/os/hal/hal.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/platform.mk
+include $(CHIBIOS_CONTRIB)/os/hal/hal.mk
+include $(CHIBIOS_CONTRIB)/os/hal/ports/STM32/STM32F1xx/platform.mk
+#include $(CHIBIOS)/os/hal/hal.mk
+#include $(CHIBIOS)/os/hal/ports/STM32/STM32F1xx/platform.mk
 include board/board.mk
 include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
 # RTOS files (optional).

board/board.h

@@ -55,9 +55,6 @@
 #define LINE_RELAY	  PAL_LINE(GPIOA, 0U)
 #define LINE_SSR		  PAL_LINE(GPIOA, 1U)
 
-#define LINE_STAB_OFF	    PAL_LINE(GPIOA, 2U)
-#define LINE_RAZGON_OFF	  PAL_LINE(GPIOA, 3U)
-
 /* Buttons */
 #define LINE_BTN_3	  PAL_LINE(GPIOA, 8U)
 #define LINE_BTN_4    PAL_LINE(GPIOB, 15U)
@@ -81,21 +78,21 @@
 /* J1 connector */
 
 // pin 1:       VBAT - Coin Cell 3V
-#define GPIOC_TAMPER_RTC        13      // pin 2
+#define GPIOC_TAMPER_RTC        13      // pin 2 Internal LED
 #define GPIOC_OSC32_IN          14      // pin 3
 #define GPIOC_OSD32_OUT         15      // pin 4
 #define GPIOA_USART2_CTS        0       // pin 5  RELAY
 #define GPIOA_USART2_RTS        1       // pin 6  SSR
-#define GPIOA_USART2_TX         2       // pin 7  STAB_OFF
-#define GPIOA_USART2_RX         3       // pin 8  RAZGON_OFF
+#define GPIOA_PIN2              2       // pin 7  USART2_TX/ADC12_IN2/TIM2_CH3
+#define GPIOA_PIN3              3       // pin 8  USART2_RX/ADC12_IN3/TIM2_CH4
 #define GPIOA_SPI1_NSS          4       // pin 9  LCD_CS
 #define GPIOA_SPI1_SCK          5       // pin 10 LCD_SCL
 #define GPIOA_SPI1_MISO         6       // pin 11 LCD_DC
 #define GPIOA_SPI1_MOSI         7       // pin 12 LCD_SDA
-#define GPIOB_ADC12_IN8         0       // pin 13
+#define GPIOB_PIN0              0       // pin 13 ADC12_IN8/TI  M3_CH3/TIM1_CH2N
 #define GPIOB_ADC12_IN9         1       // pin 14 ADC_IN
-#define GPIOB_I2C2_SCL          10      // pin 15
-#define GPIOB_I2C2_SDA          11      // pin 16
+#define GPIOB_PIN10             10      // pin 15 I2C2_SCL/USART3_TX/TIM2_CH3
+#define GPIOB_PIN11             11      // pin 16 I2C2_SDA/USART3_RX/TIM2_CH4
 // pin 17:       RESET
 // pin 18:       3V3
 // pin 19:       GND
@@ -111,13 +108,13 @@
 #define GPIOB_PIN7              7       // pin 6  I2C1_SDA/TIM4_CH2/USART1_RX
 #define GPIOB_PIN6              6       // pin 7  I2C1_SCL/TIM4_CH1/USART1_TX
 #define GPIOB_PIN5              5       // pin 8  I2C1_SMBA/TIM3_CH2/SPI1_MOSI
-#define GPIOB_JTRST             4       // pin 9  TIM3_CH1/PB4/SPI1_MISO
-#define GPIOB_JTDO              3       // pin 10 TIM2_CH2/PB3/TRACESWO/SPI1_SCK
-#define GPIOA_JTDI              15      // pin 11
-#define GPIOA_USBDP             12      // pin 12
-#define GPIOA_USBDM             11      // pin 13
-#define GPIOA_USART1_RX         10      // pin 14
-#define GPIOA_USART1_TX         9       // pin 15
+#define GPIOB_PIN4              4       // pin 9  TIM3_CH1/PB4/SPI1_MISO/JTRST
+#define GPIOB_PIN3              3       // pin 10 TIM2_CH2/PB3/TRACESWO/SPI1_SCK/JTDO
+#define GPIOA_PIN15             15      // pin 11 TIM2_CH1_ETR/SPI1_NSS/JTDI
+#define GPIOA_USBDP             12      // pin 12 USART1_RTS/CANTX/TIM1_ETR
+#define GPIOA_USBDM             11      // pin 13 USART1_CTS/CANRX/TIM1_CH4
+#define GPIOA_USART1_RX         10      // pin 14 TIM1_CH3
+#define GPIOA_USART1_TX         9       // pin 15 TIM1_CH2
 #define GPIOA_USART1_CK         8       // pin 16 BTN_4
 #define GPIOB_SPI2_MOSI         15      // pin 17 BTN_3
 #define GPIOB_SPI2_MISO         14      // pin 18 BTN_2
@@ -153,8 +150,6 @@
  * Everything input with pull-up except:
  * PA0  - Push Pull output   (LCD_RELAY).
  * PA1  - Push Pull output   (LCD_SSR).
- * PA2  - Input with Pull-Up (STAB_OFF)
- * PA3  - Input with Pull-Up (RAZGON_OFF)
  * PA4  - Push Pull output   (LCD_CS).
  * PA5  - Alternate output   (LCD_SCL - SPI1 SCK).
  * PA6  - Push Pull output   (LCD_DC).

cfg/halconf.h

@@ -79,7 +79,7 @@
  * @brief   Enables the GPT subsystem.
  */
 #if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
-#define HAL_USE_GPT                         TRUE
+#define HAL_USE_GPT                         FALSE
 #endif
 
 /**
@@ -121,7 +121,7 @@
  * @brief   Enables the PWM subsystem.
  */
 #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
-#define HAL_USE_PWM                         FALSE
+#define HAL_USE_PWM                         TRUE
 #endif
 
 /**
@@ -548,6 +548,8 @@
 #define WSPI_USE_MUTUAL_EXCLUSION           FALSE
 #endif
 
+#include "halconf_community.h"
+
 #endif /* HALCONF_H */
 
 /** @} */

cfg/halconf_community.h

@@ -0,0 +1,187 @@
+/*
+    ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef HALCONF_COMMUNITY_H
+#define HALCONF_COMMUNITY_H
+
+/**
+ * @brief   Enables the community overlay.
+ */
+#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
+#define HAL_USE_COMMUNITY           TRUE
+#endif
+
+/**
+ * @brief   Enables the FSMC subsystem.
+ */
+#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
+#define HAL_USE_FSMC                FALSE
+#endif
+
+/**
+ * @brief   Enables the SDRAM subsystem.
+ */
+#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__)
+#define HAL_USE_SDRAM               FALSE
+#endif
+
+/**
+ * @brief   Enables the SRAM subsystem.
+ */
+#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__)
+#define HAL_USE_SRAM                FALSE
+#endif
+
+/**
+ * @brief   Enables the NAND subsystem.
+ */
+#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
+#define HAL_USE_NAND                FALSE
+#endif
+
+/**
+ * @brief   Enables the 1-wire subsystem.
+ */
+#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
+#define HAL_USE_ONEWIRE             TRUE
+#endif
+
+/**
+ * @brief   Enables the EICU subsystem.
+ */
+#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
+#define HAL_USE_EICU                FALSE
+#endif
+
+/**
+ * @brief   Enables the CRC subsystem.
+ */
+#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
+#define HAL_USE_CRC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the RNG subsystem.
+ */
+#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
+#define HAL_USE_RNG                 FALSE
+#endif
+
+/**
+ * @brief   Enables the EEPROM subsystem.
+ */
+#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)
+#define HAL_USE_EEPROM              FALSE
+#endif
+
+/**
+ * @brief   Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)
+#define HAL_USE_TIMCAP              FALSE
+#endif
+
+/**
+ * @brief   Enables the TIMCAP subsystem.
+ */
+#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__)
+#define HAL_USE_COMP                FALSE
+#endif
+
+/**
+ * @brief   Enables the QEI subsystem.
+ */
+#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__)
+#define HAL_USE_QEI                 FALSE
+#endif
+
+/**
+ * @brief   Enables the USBH subsystem.
+ */
+#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__)
+#define HAL_USE_USBH                FALSE
+#endif
+
+/**
+ * @brief   Enables the USB_MSD subsystem.
+ */
+#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__)
+#define HAL_USE_USB_MSD             FALSE
+#endif
+
+/*===========================================================================*/
+/* FSMCNAND driver related settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define NAND_USE_MUTUAL_EXCLUSION   TRUE
+#endif
+
+/*===========================================================================*/
+/* 1-wire driver related settings.                                           */
+/*===========================================================================*/
+/**
+ * @brief   Enables strong pull up feature.
+ * @note    Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_STRONG_PULLUP   FALSE
+
+/**
+ * @brief   Enables search ROM feature.
+ * @note    Disabling this option saves both code and data space.
+ */
+#define ONEWIRE_USE_SEARCH_ROM      TRUE
+
+/*===========================================================================*/
+/* QEI driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables discard of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_DISCARD    FALSE
+#endif
+
+/**
+ * @brief   Enables min max of overlow
+ */
+#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__)
+#define QEI_USE_OVERFLOW_MINMAX     FALSE
+#endif
+
+/*===========================================================================*/
+/* EEProm driver related settings.                                           */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables 24xx series I2C eeprom device driver.
+ * @note    Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE24XX FALSE
+ /**
+ * @brief   Enables 25xx series SPI eeprom device driver.
+ * @note    Disabling this option saves both code and data space.
+ */
+#define EEPROM_USE_EE25XX FALSE
+
+#endif /* HALCONF_COMMUNITY_H */
+
+/** @} */

cfg/mcuconf.h

@@ -89,7 +89,7 @@
  */
 #define STM32_GPT_USE_TIM1                  FALSE
 #define STM32_GPT_USE_TIM2                  FALSE
-#define STM32_GPT_USE_TIM3                  TRUE
+#define STM32_GPT_USE_TIM3                  FALSE
 #define STM32_GPT_USE_TIM4                  FALSE
 #define STM32_GPT_USE_TIM5                  FALSE
 #define STM32_GPT_USE_TIM8                  FALSE
@@ -134,7 +134,7 @@
 #define STM32_PWM_USE_ADVANCED              FALSE
 #define STM32_PWM_USE_TIM1                  FALSE
 #define STM32_PWM_USE_TIM2                  FALSE
-#define STM32_PWM_USE_TIM3                  FALSE
+#define STM32_PWM_USE_TIM3                  TRUE
 #define STM32_PWM_USE_TIM4                  FALSE
 #define STM32_PWM_USE_TIM5                  FALSE
 #define STM32_PWM_USE_TIM8                  FALSE
@@ -211,4 +211,6 @@
  */
 #define STM32_WDG_USE_IWDG                  FALSE
 
+#include "mcuconf_community.h"
+
 #endif /* MCUCONF_H */

cfg/mcuconf_community.h

@@ -0,0 +1,157 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * FSMC driver system settings.
+ */
+#define STM32_FSMC_USE_FSMC1                FALSE
+#define STM32_FSMC_FSMC1_IRQ_PRIORITY       10
+
+/*
+ * FSMC NAND driver system settings.
+ */
+#define STM32_NAND_USE_NAND1           FALSE
+#define STM32_NAND_USE_NAND2           FALSE
+#define STM32_NAND_USE_EXT_INT              FALSE
+#define STM32_NAND_DMA_STREAM               STM32_DMA_STREAM_ID(2, 7)
+#define STM32_NAND_DMA_PRIORITY             0
+#define STM32_NAND_DMA_ERROR_HOOK(nandp)    osalSysHalt("DMA failure")
+
+/*
+ * FSMC SRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SRAM                 FALSE
+#define STM32_SRAM_USE_FSMC_SRAM1           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM2           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM3           FALSE
+#define STM32_SRAM_USE_FSMC_SRAM4           FALSE
+
+/*
+ * FSMC SDRAM driver system settings.
+ */
+#define STM32_USE_FSMC_SDRAM                FALSE
+#define STM32_SDRAM_USE_FSMC_SDRAM1         FALSE
+#define STM32_SDRAM_USE_FSMC_SDRAM2         FALSE
+
+/*
+ * TIMCAP driver system settings.
+ */
+#define STM32_TIMCAP_USE_TIM1                  FALSE
+#define STM32_TIMCAP_USE_TIM2                  FALSE
+#define STM32_TIMCAP_USE_TIM3                  FALSE
+#define STM32_TIMCAP_USE_TIM4                  FALSE
+#define STM32_TIMCAP_USE_TIM5                  FALSE
+#define STM32_TIMCAP_USE_TIM8                  FALSE
+#define STM32_TIMCAP_USE_TIM9                  FALSE
+#define STM32_TIMCAP_TIM1_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM2_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM3_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM4_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM5_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM8_IRQ_PRIORITY         3
+#define STM32_TIMCAP_TIM9_IRQ_PRIORITY         3
+
+/*
+ * COMP driver system settings.
+ */
+#define STM32_COMP_USE_COMP1                  FALSE
+#define STM32_COMP_USE_COMP2                  FALSE
+#define STM32_COMP_USE_COMP3                  FALSE
+#define STM32_COMP_USE_COMP4                  FALSE
+#define STM32_COMP_USE_COMP5                  FALSE
+#define STM32_COMP_USE_COMP6                  FALSE
+#define STM32_COMP_USE_COMP7                  FALSE
+
+#define STM32_COMP_USE_INTERRUPTS             FALSE
+#define STM32_COMP_1_2_3_IRQ_PRIORITY         5
+#define STM32_COMP_4_5_6_IRQ_PRIORITY         5
+#define STM32_COMP_7_IRQ_PRIORITY             5
+
+#if STM32_COMP_USE_INTERRUPTS
+#define STM32_DISABLE_EXTI21_22_29_HANDLER
+#define STM32_DISABLE_EXTI30_32_HANDLER
+#define STM32_DISABLE_EXTI33_HANDLER
+#endif
+
+/*
+ * USBH driver system settings.
+ */
+#define STM32_OTG_FS_CHANNELS_NUMBER          8
+#define STM32_OTG_HS_CHANNELS_NUMBER          12
+
+#define STM32_USBH_USE_OTG1                 1
+#define STM32_OTG_FS_RXFIFO_SIZE              1024
+#define STM32_OTG_FS_PTXFIFO_SIZE             128
+#define STM32_OTG_FS_NPTXFIFO_SIZE            128
+
+#define STM32_USBH_USE_OTG2                 0
+#define STM32_OTG_HS_RXFIFO_SIZE              2048
+#define STM32_OTG_HS_PTXFIFO_SIZE             1024
+#define STM32_OTG_HS_NPTXFIFO_SIZE            1024
+
+#define STM32_USBH_MIN_QSPACE               4
+#define STM32_USBH_CHANNELS_NP              4
+
+/*
+ * CRC driver system settings.
+ */
+#define STM32_CRC_USE_CRC1                  FALSE
+#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY     1
+#define STM32_CRC_CRC1_DMA_PRIORITY         2
+#define STM32_CRC_CRC1_DMA_STREAM           STM32_DMA1_STREAM2
+
+#define CRCSW_USE_CRC1                      FALSE
+#define CRCSW_CRC32_TABLE                   FALSE
+#define CRCSW_CRC16_TABLE                   FALSE
+#define CRCSW_PROGRAMMABLE                  FALSE
+
+/*
+ * EICU driver system settings.
+ */
+#define STM32_EICU_USE_TIM1                 FALSE
+#define STM32_EICU_USE_TIM2                 FALSE
+#define STM32_EICU_USE_TIM3                 FALSE
+#define STM32_EICU_USE_TIM4                 FALSE
+#define STM32_EICU_USE_TIM5                 FALSE
+#define STM32_EICU_USE_TIM8                 FALSE
+#define STM32_EICU_USE_TIM9                 FALSE
+#define STM32_EICU_USE_TIM10                FALSE
+#define STM32_EICU_USE_TIM11                FALSE
+#define STM32_EICU_USE_TIM12                FALSE
+#define STM32_EICU_USE_TIM13                FALSE
+#define STM32_EICU_USE_TIM14                FALSE
+#define STM32_EICU_TIM1_IRQ_PRIORITY        7
+#define STM32_EICU_TIM2_IRQ_PRIORITY        7
+#define STM32_EICU_TIM3_IRQ_PRIORITY        7
+#define STM32_EICU_TIM4_IRQ_PRIORITY        7
+#define STM32_EICU_TIM5_IRQ_PRIORITY        7
+#define STM32_EICU_TIM8_IRQ_PRIORITY        7
+#define STM32_EICU_TIM9_IRQ_PRIORITY        7
+#define STM32_EICU_TIM10_IRQ_PRIORITY       7
+#define STM32_EICU_TIM11_IRQ_PRIORITY       7
+#define STM32_EICU_TIM12_IRQ_PRIORITY       7
+#define STM32_EICU_TIM13_IRQ_PRIORITY       7
+#define STM32_EICU_TIM14_IRQ_PRIORITY       7
+
+/*
+ * QEI driver system settings.
+ */
+#define STM32_QEI_USE_TIM1                FALSE
+#define STM32_QEI_USE_TIM2                FALSE
+#define STM32_QEI_USE_TIM3                FALSE
+#define STM32_QEI_TIM1_IRQ_PRIORITY         3
+#define STM32_QEI_TIM2_IRQ_PRIORITY         3
+#define STM32_QEI_TIM3_IRQ_PRIORITY         3

lib/lib.mk

@@ -6,13 +6,15 @@ USERSRC =  $(USERLIB)/st7735/st7735.c \
 	$(USERLIB)/st7735/fonts.c \
 	$(USERLIB)/st7735/liberation_mono_7x10.c \
 	$(USERLIB)/st7735/font_12x16uk.c \
-	$(USERLIB)/buttons/buttons.c
+	$(USERLIB)/buttons/buttons.c \
+	$(USERLIB)/onewire/testhal_onewire.c
           
 # Required include directories
 USERINC =  $(USERLIB) \
            $(USERLIB)/st7735 \
            $(USERLIB)/eeprom \
-           $(USERLIB)/buttons
+           $(USERLIB)/buttons \
+           $(USERLIB)/onewire
 
 # Shared variables
 ALLCSRC += $(USERSRC)

lib/onewire/boarddef.h

@@ -0,0 +1,29 @@
+/*
+    ChibiOS/RT - Copyright (C) 2016 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef BOARDDEF_H_
+#define BOARDDEF_H_
+
+#define ONEWIRE_PORT                  GPIOB
+#define ONEWIRE_PIN                   0
+#define ONEWIRE_PAD_MODE_IDLE         PAL_MODE_INPUT
+#define ONEWIRE_PAD_MODE_ACTIVE       PAL_MODE_STM32_ALTERNATE_OPENDRAIN
+#define search_led_on()               (palClearPad(GPIOC, GPIOC_LED))
+#define search_led_off()              (palSetPad(GPIOC, GPIOC_LED))
+#define ONEWIRE_MASTER_CHANNEL        2
+#define ONEWIRE_SAMPLE_CHANNEL        3
+
+#endif /* BOARDDEF_H_ */

lib/onewire/synth_searchrom.c

@@ -0,0 +1,370 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include <stdlib.h>
+
+/*
+ ******************************************************************************
+ * DEFINES
+ ******************************************************************************
+ */
+
+/* do not set it more than 64 because of some fill_pattern functions
+   will be broken.*/
+#define SYNTH_DEVICES_MAX     64
+
+/*
+ * synthetic device
+ */
+typedef struct {
+  bool      active;
+  uint64_t  id;
+} OWSynthDevice;
+
+/*
+ * synthetic bus
+ */
+typedef struct {
+  OWSynthDevice   devices[SYNTH_DEVICES_MAX];
+  size_t          dev_present;
+  bool            complement_bit;
+  ioline_t        rom_bit;
+} OWSynthBus;
+
+/*
+ ******************************************************************************
+ * EXTERNS
+ ******************************************************************************
+ */
+
+/*
+ ******************************************************************************
+ * PROTOTYPES
+ ******************************************************************************
+ */
+
+/*
+ ******************************************************************************
+ * GLOBAL VARIABLES
+ ******************************************************************************
+ */
+
+static OWSynthBus synth_bus;
+
+/*
+ * local buffer for discovered ROMs
+ */
+static uint64_t detected_devices[SYNTH_DEVICES_MAX];
+
+/*
+ ******************************************************************************
+ ******************************************************************************
+ * LOCAL FUNCTIONS
+ ******************************************************************************
+ ******************************************************************************
+ */
+
+/*
+ ******************************************************************************
+ * EXPORTED FUNCTIONS
+ ******************************************************************************
+ */
+
+/*
+ *
+ */
+void _synth_ow_write_bit(onewireDriver *owp, ioline_t bit) {
+  (void)owp;
+  size_t i;
+
+  for (i=0; i<SYNTH_DEVICES_MAX; i++) {
+    if (((synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U) != bit) {
+      synth_bus.devices[i].active = false;
+    }
+  }
+  synth_bus.rom_bit++;
+}
+
+/*
+ *
+ */
+ioline_t _synth_ow_read_bit(void) {
+  ioline_t ret = 0xFF;
+  size_t i;
+  ioline_t bit;
+
+  for (i=0; i<SYNTH_DEVICES_MAX; i++) {
+    if (synth_bus.devices[i].active){
+      bit = (synth_bus.devices[i].id >> synth_bus.rom_bit) & 1U;
+      if (synth_bus.complement_bit){
+        bit ^= 1U;
+      }
+      if (0xFF == ret)
+        ret = bit;
+      else
+        ret &= bit;
+    }
+  }
+  synth_bus.complement_bit = !synth_bus.complement_bit;
+  return ret;
+}
+
+/*
+ *
+ */
+static void synth_reset_pulse(void){
+  size_t i;
+
+  for (i=0; i<synth_bus.dev_present; i++){
+    synth_bus.devices[i].active = true;
+  }
+}
+
+/*
+ *
+ */
+static size_t synth_search_rom(onewireDriver *owp, uint8_t *result, size_t max_rom_cnt) {
+
+  size_t i;
+
+  search_clean_start(&owp->search_rom);
+
+  do {
+    /* initialize buffer to store result */
+    if (owp->search_rom.reg.devices_found >= max_rom_cnt)
+      owp->search_rom.retbuf = result + 8*(max_rom_cnt-1);
+    else
+      owp->search_rom.retbuf = result + 8*owp->search_rom.reg.devices_found;
+    memset(owp->search_rom.retbuf, 0, 8);
+
+    /* clean iteration state */
+    search_clean_iteration(&owp->search_rom);
+
+    /**/
+    synth_reset_pulse();
+    synth_bus.rom_bit = 0;
+    synth_bus.complement_bit = false;
+    for (i=0; i<64*3 - 1; i++){
+      ow_search_rom_cb(NULL, owp);
+    }
+
+    if (ONEWIRE_SEARCH_ROM_ERROR != owp->search_rom.reg.result) {
+      /* store cached result for usage in next iteration */
+      memcpy(owp->search_rom.prev_path, owp->search_rom.retbuf, 8);
+    }
+  }
+  while (ONEWIRE_SEARCH_ROM_SUCCESS == owp->search_rom.reg.result);
+
+  /**/
+  if (ONEWIRE_SEARCH_ROM_ERROR == owp->search_rom.reg.result)
+    return 0;
+  else
+    return owp->search_rom.reg.devices_found;
+}
+
+/*
+ *
+ */
+static void fill_pattern_real_devices(void) {
+  size_t i;
+
+  for (i=0; i<SYNTH_DEVICES_MAX; i++)
+    synth_bus.devices[i].active = false;
+
+  synth_bus.devices[0].active = true;
+  synth_bus.devices[0].id = 0x1d00000567f5ec28;
+
+  synth_bus.devices[1].active = true;
+  synth_bus.devices[1].id = 0x37000005601abd28;
+
+  synth_bus.devices[2].active = true;
+  synth_bus.devices[2].id = 0x0f000005677d8328;
+}
+
+/*
+ *
+ */
+static void fill_pattern_00(size_t devices, size_t start) {
+  size_t i;
+
+  for (i=0; i<SYNTH_DEVICES_MAX; i++)
+    synth_bus.devices[i].active = false;
+
+  for (i=0; i<devices; i++){
+    synth_bus.devices[i].active = true;
+    synth_bus.devices[i].id = (start + i);
+  }
+}
+
+/*
+ *
+ */
+static void fill_pattern_01(size_t devices) {
+  size_t i;
+
+  for (i=0; i<SYNTH_DEVICES_MAX; i++)
+    synth_bus.devices[i].active = false;
+
+  for (i=0; i<devices; i++){
+    synth_bus.devices[i].active = true;
+    synth_bus.devices[i].id = (devices - i);
+  }
+}
+
+/*
+ *
+ */
+static void fill_pattern_02(size_t devices) {
+  size_t i;
+
+  for (i=0; i<SYNTH_DEVICES_MAX; i++)
+    synth_bus.devices[i].active = false;
+
+  for (i=0; i<devices; i++){
+    synth_bus.devices[i].active = true;
+    synth_bus.devices[i].id = ((uint64_t)1 << i);
+  }
+}
+
+/*
+ *
+ */
+static void fill_pattern_03(size_t devices) {
+  size_t i;
+
+  for (i=0; i<SYNTH_DEVICES_MAX; i++)
+    synth_bus.devices[i].active = false;
+
+  for (i=0; i<devices; i++){
+    synth_bus.devices[i].active = true;
+    synth_bus.devices[i].id = ((uint64_t)0x8000000000000000 >> i);
+  }
+}
+
+/*
+ * Random pattern helper
+ */
+static bool is_id_uniq(const OWSynthDevice *dev, size_t n, uint64_t id) {
+  size_t i;
+
+  for (i=0; i<n; i++) {
+    if (dev[i].id == id)
+      return false;
+  }
+  return true;
+}
+
+/*
+ *
+ */
+static void fill_pattern_rand(size_t devices) {
+  size_t i;
+  uint64_t new_id;
+
+  for (i=0; i<SYNTH_DEVICES_MAX; i++){
+    synth_bus.devices[i].active = false;
+    synth_bus.devices[i].id = 0;
+  }
+
+  for (i=0; i<devices; i++) {
+    do {
+      new_id = rand();
+      new_id = (new_id << 32) | rand();
+    } while (true != is_id_uniq(synth_bus.devices, i, new_id));
+
+    synth_bus.devices[i].id = new_id;
+    synth_bus.devices[i].active = true;
+  }
+}
+
+/*
+ *
+ */
+static bool check_result(size_t detected) {
+
+  size_t i,j;
+  bool match = false;
+
+  for (i=0; i<detected; i++){
+    match = false;
+    for (j=0; j<detected; j++){
+      if (synth_bus.devices[i].id == detected_devices[j]){
+        match = true;
+        break;
+      }
+    }
+    if (false == match)
+      return OSAL_FAILED;
+  }
+  return OSAL_SUCCESS;
+}
+
+/*
+ *
+ */
+void synthSearchRomTest(onewireDriver *owp) {
+
+  size_t detected = 0;
+  size_t i;
+
+  synth_bus.dev_present = 3;
+  fill_pattern_real_devices();
+  detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX);
+  osalDbgCheck(synth_bus.dev_present == detected);
+  osalDbgCheck(OSAL_SUCCESS == check_result(detected));
+
+  for (i=1; i<=SYNTH_DEVICES_MAX; i++){
+    synth_bus.dev_present = i;
+
+    fill_pattern_00(synth_bus.dev_present, 0);
+    detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX);
+    osalDbgCheck(synth_bus.dev_present == detected);
+    osalDbgCheck(OSAL_SUCCESS == check_result(detected));
+
+    fill_pattern_00(synth_bus.dev_present, 1);
+    detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX);
+    osalDbgCheck(synth_bus.dev_present == detected);
+    osalDbgCheck(OSAL_SUCCESS == check_result(detected));
+
+    fill_pattern_01(synth_bus.dev_present);
+    detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX);
+    osalDbgCheck(synth_bus.dev_present == detected);
+    osalDbgCheck(OSAL_SUCCESS == check_result(detected));
+
+    fill_pattern_02(synth_bus.dev_present);
+    detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX);
+    osalDbgCheck(synth_bus.dev_present == detected);
+    osalDbgCheck(OSAL_SUCCESS == check_result(detected));
+
+    fill_pattern_03(synth_bus.dev_present);
+    detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX);
+    osalDbgCheck(synth_bus.dev_present == detected);
+    osalDbgCheck(OSAL_SUCCESS == check_result(detected));
+  }
+
+  i = 0;
+  while (i < 1000) {
+    synth_bus.dev_present = 1 + (rand() & 63);
+
+    fill_pattern_rand(synth_bus.dev_present);
+    detected = synth_search_rom(owp, (uint8_t *)detected_devices, SYNTH_DEVICES_MAX);
+    osalDbgCheck(synth_bus.dev_present == detected);
+    osalDbgCheck(OSAL_SUCCESS == check_result(detected));
+    i++;
+  }
+}
+
+

lib/onewire/testhal_onewire.c

@@ -0,0 +1,227 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include <string.h>
+
+#include "hal.h"
+#include "boarddef.h"
+
+/*
+ ******************************************************************************
+ * DEFINES
+ ******************************************************************************
+ */
+
+/*
+ ******************************************************************************
+ * EXTERNS
+ ******************************************************************************
+ */
+
+/*
+ ******************************************************************************
+ * PROTOTYPES
+ ******************************************************************************
+ */
+/*
+ * Forward declarations
+ */
+#if ONEWIRE_USE_STRONG_PULLUP
+static void strong_pullup_assert(void);
+static void strong_pullup_release(void);
+#endif
+
+/*
+ ******************************************************************************
+ * GLOBAL VARIABLES
+ ******************************************************************************
+ */
+
+static uint8_t testbuf[12];
+
+/* stores 3 temperature values in millicelsius */
+static int32_t temperature[3];
+static size_t devices_on_bus = 0;
+
+/*
+ * Config for underlying PWM driver.
+ * Note! It is NOT constant because 1-wire driver needs to change them
+ * during functioning.
+ */
+static PWMConfig pwm_cfg = {
+    0,
+    0,
+    NULL,
+    {
+     {PWM_OUTPUT_DISABLED, NULL},
+     {PWM_OUTPUT_DISABLED, NULL},
+     {PWM_OUTPUT_DISABLED, NULL},
+     {PWM_OUTPUT_DISABLED, NULL}
+    },
+    0,
+#if STM32_PWM_USE_ADVANCED
+    0,
+#endif
+    0,
+    0
+};
+
+/*
+ *
+ */
+static const onewireConfig ow_cfg = {
+    &PWMD3,
+    &pwm_cfg,
+    PWM_OUTPUT_ACTIVE_LOW,
+    ONEWIRE_MASTER_CHANNEL,
+    ONEWIRE_SAMPLE_CHANNEL,
+    ONEWIRE_PORT,
+    ONEWIRE_PIN,
+#if defined(STM32F1XX)
+    ONEWIRE_PAD_MODE_IDLE,
+#endif
+    ONEWIRE_PAD_MODE_ACTIVE,
+#if ONEWIRE_USE_STRONG_PULLUP
+    strong_pullup_assert,
+    strong_pullup_release
+#endif
+};
+
+/*
+ ******************************************************************************
+ ******************************************************************************
+ * LOCAL FUNCTIONS
+ ******************************************************************************
+ ******************************************************************************
+ */
+
+#if ONEWIRE_USE_STRONG_PULLUP
+/**
+ *
+ */
+static void strong_pullup_assert(void) {
+  palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+}
+
+/**
+ *
+ */
+static void strong_pullup_release(void) {
+  palSetPadMode(ONEWIRE_PORT, ONEWIRE_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
+}
+#endif /* ONEWIRE_USE_STRONG_PULLUP */
+
+/*
+ ******************************************************************************
+ * EXPORTED FUNCTIONS
+ ******************************************************************************
+ */
+
+/*
+ *
+ */
+void onewireTest(void) {
+
+  int16_t tmp;
+  uint8_t rombuf[24];
+  size_t i = 0;
+  bool presence;
+
+  onewireObjectInit(&OWD1);
+  onewireStart(&OWD1, &ow_cfg);
+
+#if ONEWIRE_SYNTH_SEARCH_TEST
+  synthSearchRomTest(&OWD1);
+#endif
+
+  for (i=0; i<3; i++)
+    temperature[i] = -666;
+
+  while (true) {
+    if (true == onewireReset(&OWD1)){
+
+      memset(rombuf, 0x55, sizeof(rombuf));
+      search_led_on();
+      devices_on_bus = onewireSearchRom(&OWD1, rombuf, 3);
+      search_led_off();
+      osalDbgCheck(devices_on_bus <= 3);
+      osalDbgCheck(devices_on_bus  > 0);
+
+      if (1 == devices_on_bus){
+        /* test read rom command */
+        presence = onewireReset(&OWD1);
+        osalDbgCheck(true == presence);
+        testbuf[0] = ONEWIRE_CMD_READ_ROM;
+        onewireWrite(&OWD1, testbuf, 1, 0);
+        onewireRead(&OWD1, testbuf, 8);
+        osalDbgCheck(testbuf[7] == onewireCRC(testbuf, 7));
+        osalDbgCheck(0 == memcmp(rombuf, testbuf, 8));
+      }
+
+      /* start temperature measurement on all connected devices at once */
+      presence = onewireReset(&OWD1);
+      osalDbgCheck(true == presence);
+      testbuf[0] = ONEWIRE_CMD_SKIP_ROM;
+      testbuf[1] = ONEWIRE_CMD_CONVERT_TEMP;
+
+#if ONEWIRE_USE_STRONG_PULLUP
+      onewireWrite(&OWD1, testbuf, 2, TIME_MS2I(750));
+#else
+      onewireWrite(&OWD1, testbuf, 2, 0);
+      /* poll bus waiting ready signal from all connected devices */
+      testbuf[0] = 0;
+      while (testbuf[0] == 0){
+        osalThreadSleepMilliseconds(50);
+        onewireRead(&OWD1, testbuf, 1);
+      }
+#endif
+
+      for (i=0; i<devices_on_bus; i++) {
+        /* read temperature device by device from their scratchpads */
+        presence = onewireReset(&OWD1);
+        osalDbgCheck(true == presence);
+
+        testbuf[0] = ONEWIRE_CMD_MATCH_ROM;
+        memcpy(&testbuf[1], &rombuf[i*8], 8);
+        testbuf[9] = ONEWIRE_CMD_READ_SCRATCHPAD;
+        onewireWrite(&OWD1, testbuf, 10, 0);
+
+        onewireRead(&OWD1, testbuf, 9);
+        osalDbgCheck(testbuf[8] == onewireCRC(testbuf, 8));
+        memcpy(&tmp, &testbuf, 2);
+        temperature[i] = ((int32_t)tmp * 625) / 10;
+      }
+    }
+    else {
+      devices_on_bus = 0;
+    }
+    osalThreadSleep(1); /* enforce ChibiOS's stack overflow check */
+  }
+
+  onewireStop(&OWD1);
+}
+
+uint8_t onewireGetDevicesNum(void) {
+  return (uint8_t)devices_on_bus;
+}
+
+int32_t onewireGetTemperature(const size_t num) {
+  if (num > devices_on_bus || num < devices_on_bus) {
+    return -999;
+  } else {
+    return temperature[num];
+  }
+}

lib/onewire/testhal_onewire.h

@@ -0,0 +1,30 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef TESTHAL_ONEWIRE_H_
+#define TESTHAL_ONEWIRE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void onewireTest(void);
+  uint8_t onewireGetDevicesNum(void);
+  int32_t onewireGetTemperature(size_t num);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TESTHAL_ONEWIRE_H_ */

main.c

@@ -24,6 +24,7 @@
 
 #include "main.h"
 #include "st7735.h"
+#include "testhal_onewire.h"
 
 /*===========================================================================*/
 /* Generic code.                                                             */
@@ -49,6 +50,7 @@ static __attribute__((noreturn)) THD_FUNCTION(Thread1, arg) {
  * Application entry point.
  */
 int main(void) {
+  char buf[24];
   /*
    * System initializations.
    * - HAL initialization, this also initializes the configured device drivers
@@ -87,6 +89,16 @@ int main(void) {
   /*
    * Normal main() thread activity.
    */
+  onewireTest();
+  int n = onewireGetDevicesNum();
+  if (n != 0) {
+    int32_t t = onewireGetTemperature(1);
+    chsnprintf(buf, 22, "    T = %d °C     ", t);
+    ST7735_WriteString(0, 20, buf, LiberM_7x10, Yellow, Black);
+  } else {
+    ST7735_WriteString(0, 20, "DS18B20 not found.", LiberM_7x10, Red, Black);
+  }
+
   while (true) {
     chThdSleepMilliseconds(500);
   }