/*
 * dieses File definiert die Regeln für die Interrupts
|  Der STM hat 4bits = 16 Prioritäten zu vergeben, die nochmals in Group- und Sub-Prio unterteilt werden.
|  Group-Prio Interrupts können sich jeweils unterbrechen, Sub-Prio-Interrupts werden
|  nur verschachtelt ausgeführt. Verschachtelte Interrupts können die gleiche HW resource benutzen.
|
| Es gibt bei ST PRIGROUP3 - PRIGROUP7
| Wir legen PRIGROUP4 fest, das heißt, jede 2. Prio-Stufe ist eine neue Group-Prio.
|
| printf_() kann im Interrupt verwendet werden, wird aber evtl. unterdrückt, wenn printf_() gerade
| in Benutzung ist.
| glcd_printf() sollte nicht im Interrupt verwendet werden, da der Port E auch anderweitig verwendet
| wird.
| SysTick_IRQn hat noch eine besondere Priorität.
|
*/

//#define STM32F10X_MD
#include "config.h"  // controller type selects 1 or 2 ADC's
#include "stm32f10x.h"


/* =============================================================================+
* system settings
* \details Configures Flash latency (wait-states) which allows the chip to run
* ==============================================================================*/

#undef FLASH_WAIT_STATES
#if (FREQUENCY < 24000000ul)        // 0 wait states for core speed below 24MHz
   #define FLASH_WAIT_STATES 0
#elif (FREQUENCY < 48000000ul)		// 1 wait state for core speed between 24MHz and 48MHz
   #define FLASH_WAIT_STATES 1
#else									      // 2 wait states for core speed over 48MHz
   #define FLASH_WAIT_STATES 2
#endif


#undef PLLMUL
#if (SYSCLK/CRYSTAL >= 2)        // 0 wait states for core speed below 24MHz
   #define PLLMUL  (SYSCLK/CRYSTAL - 2) & 0x0F
#else									      // 2 wait states for core speed over 48MHz
   #define PLLMUL   0
#endif


/*------------------------------------------------------------------------*//**
* \brief Starts the PLL
* \details Configure and enable PLL to achieve some frequency with some crystal.
* Before the speed change Flash latency is configured via flash_latency(). PLL
* parameter mul is based on both function parameters. The PLL is set up,
* started and connected. APB1 clock ratio is set to 1:2 (max freq = 36MHz)
*
* \param [in] crystal is the frequency of the crystal resonator connected to the
* STM32F101VB
* \param [in] frequency is the desired target frequency after enabling the PLL
*//*-------------------------------------------------------------------------*/

void pll_start()
{
//	unsigned int PLLmul;


/*	PLLmul = frequency / crystal;			  // PLL multiplier calculation

   if (PLLmul > 2) PLLmul = (PLLmul-2)&0x0F; //4bit
   else PLLmul=0;
*/
	FLASH->ACR |= FLASH_WAIT_STATES;             // set fix 0, 1, 2 wait states; config.c

	RCC->CR  |= RCC_CR_HSEON;			  // enable HSE clock,  STM original, braucht 10 byte mehr code!
	while (((RCC->CR) & RCC_CR_HSERDY)==0);			  // wait for stable clock

	RCC->CFGR = (PLLMUL << 18) | RCC_CFGR_PLLSRC // configuration of PLL: HSE x (mul),
            | ADC_prescaler                 // clk = APB2/2; ADC max freq. =14MHz
            | AHC_prescaler
            | APB2_prescaler                // APB2 clk = frequency;    UART1,   TIM1,  ADC1-3, GPIOA-E
            | APB1_prescaler;	              // APB1 clk = frequency/2 ; UART2-5, TIM2,TIM3,TIM4, SPI2-3

	RCC->CR  |= RCC_CR_PLLON;               //PLL einschalten STM original, braucht 10 byte mehr code!
	while (((RCC->CR) & RCC_CR_HSERDY)==0);				// wait for PLL lock

	RCC->CFGR |= RCC_CFGR_SW_PLL;			// change SYSCLK to PLL
	while (((RCC->CFGR) & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);	// wait for switch
}

/*------------------------------------------------------------------------*//**
* \brief Initializes system
* \details Enables the clock for all GPIO ports (GPIOA - GPIOE)
*//*-------------------------------------------------------------------------*/

/* static void system_init(void)
{
   //enable the clocks
	RCC->APB2ENR = RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN |
		RCC_APB2ENR_IOPDEN | RCC_APB2ENR_IOPEEN; // enable all GPIOs
}*/
