/** \file config.h
 * \brief Basic configuration of the project
 * \author Marten Petschke
 * \date   4.6.2012
 */

#ifndef CONFIG_H_
#define CONFIG_H_

#define STM32F10X_MD     //activates the right register names for STM32F101VB
//#include "stm32f10x.h"


/*
+=============================================================================+
| global definitions
+=============================================================================+
*/
//clock tree: please adapt the following lines manually:
#define CRYSTAL								8000000ul	/* < quartz crystal resonator which is connected to the chip */
#define FREQUENCY							   16000000ul	/* < desired target frequency of the core */
#define SYSCLK                         FREQUENCY
#define AHC_prescaler                  0 /*RCC_CFGR_HPRE1_DIV2*/
#define APB1_prescaler                 RCC_CFGR_PPRE1_DIV2       /* APB1 clk = frequency/2 ; UART2-5, TIM2,TIM3,TIM4,SPI2-3 */
#define APB1CLK                        8000000ul
#define APB2_prescaler                 0 /*RCC_CFGR_PPRE2_DIV2*/ /* APB2 clk = frequency; ADC1-3, TIM1, UART1, GPIOA-E*/
#define APB2CLK                        16000000ul
#define ADC_prescaler                  (AHC_prescaler | APB2_prescaler | RCC_CFGR_ADCPRE_DIV2)  /*ADC's*/



// STM32 timer bug correction "RCC_CFGR_PPRE1_DIV2 does not work correctly":
// -----------------------------------------------------------------------
//#undef APB1CLK_FOR_TIMERS
#if (SYSCLK/APB1CLK == 2)
   #define APB1CLK_FOR_TIMERS   (APB1CLK * 2) /* APB1 TIM2,TIM3,TIM4 */
#else
   #define APB1CLK_FOR_TIMERS   APB1CLK
#endif

#if (SYSCLK/APB2CLK == 2) /* APB2 TIM1*/
   #define APB2CLK_FOR_TIMERS   (APB2CLK * 2)
#else
   #define APB2CLK_FOR_TIMERS   APB2CLK
#endif
// -----------------------------------------------------------------------



#define USE_FULL_ASSERT
#define USE_DEBUG


void set_intr_prio(void);
void pll_start(void);


#endif /* CONFIG_H_ */
